LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 20

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between V
capacitor will overcome voltage slumps caused by PC
board trace inductance.
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
CC
and GND and between its V
CC
and GND. The bulk
PP
5.3 V
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V
supplies the memory cell current for byte writing and
block erasing. Use similar trace widths and layout
considerations given to the V
supply traces and decoupling will decrease V
spikes and overshoots.
5.4 V
Block erase and byte write are not guaranteed if V
outside of a valid V
valid 2.7V-3.6V range, or RP# V
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to V
reset operation will execute. Then, the operation will abort
and the device will enter deep power-down. The aborted
operation may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V
The CUI latches commands issued by system software and
is not altered by V
Its state is read array mode upon power-up, after exit from
deep power-down or after V
After block erase or byte write, even after V
down to V
mode via the Read Array command if subsequent access
to the memory array is desired.
IL
clear the status register.
PP
CC
, V
Trace on Printed Circuit Boards
PPLK
PP
, the CUI must be placed in read array
, RP# Transitions
PP
PP
IL
PPH1/2/3
or CE# transitions or WSM actions.
Power supply trace. The V
during block erase or byte write, the
CC
range, V
CC
transitions below V
power bus. Adequate V
IH
or V
CC
falls outside of a
HH
. If V
PP
PP
transitions
Rev. 1.1
PP
LKO
voltage
PP
PP
error
falls
.
pin
PP