LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 12

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

4.1 Read Array Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or byte write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Byte Write Suspend command. The
Read Array command functions independently of the V
voltage and RP# can be V
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command functions
independently of the V
V
following information can be read:
4.3 Read Status Register Command
The status register may be read to determine when a block
erase or byte write is complete and whether the operation
completed successfully. It may be read at any time by
writing the Read Status Register command. After writing
this command, all subsequent read operations output data
from the status register until another valid command is
written. The status register contents are latched on the
falling edge of OE# or CE#, whichever occurs. OE# or
CE# must toggle to V
status register latch. The Read Status Register command
functions independently of the V
V
Manufacture Code
Device Code
HH
IH
or V
. Following the Read Identifier Codes command, the
HH
.
Code
Table 5. Identifier Codes
IH
PP
before further reads to update the
IH
voltage and RP# can be V
or V
HH
[A
Address
00000H
00001H
PP
.
19
voltage. RP# can be
-A
0
]
[DQ
Data
4BH
B0H
7
-DQ
IH
0
PP
or
]
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied V
command is not functional during block erase or byte
write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the output data of the status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V
high voltage, block contents are protected against erasure.
If block erase is attempted while V
SR.5 will be set to "1". Successful block erase for boot
blocks requires that the corresponding if set, that
WP#=V
boot block when the corresponding WP#=V
RP#=V
operations with V
and should not be attempted.
CC
=2.7V-3.6V and V
IH
IH
, SR.1 and SR.5 will be set to "1". Block erase
or RP#=V
PP
Voltage. RP# can be V
IH
<RP#<V
HH
PP
. If block erase is attempted to
=V
PPH1/2/3
HH
produce spurious results
. In the absence of this
PP
V
IH
PPLK
or V
, SR.3 and
HH
Rev. 1.1
IL
. This
or