LH28F800BVHE-BTL90 Sharp Electronics, LH28F800BVHE-BTL90 Datasheet - Page 7

• Manufacturer Part Number: LH28F800BVHE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVHE-BTL90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

The boot blocks can be locked for the WP# pin. Block
erase or word/byte write for boot block must not be carried
out by WP# to Low and RP# to V
The status register indicates when the WSM’s block erase
or word/byte write operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase or word/byte
write. RY/BY#-high Z indicates that the WSM is ready for
a new command, block erase is suspended (and word/byte
write is inactive), word/byte write is suspended, or the
device is in deep power-down mode.
The access time is 90ns (t
temperature range (-40°C to +85°C) and V
voltage range of 2.7V-3.6V.
sharp
AVQV
IH
.
) over the extended
CC
supply
LHF80V13
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I
current is 3mA at 2.7V V
When CE# and RP# pins are at V
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (t
high until outputs are valid. Likewise, the device has a
wake time (t
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 48-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in Figure
2.
PHEL
) from RP#-high until writes to the CUI
PHQV
CC
) is required from RP# switching
.
CC
, the I
CC
Rev. 1.1
CMOS
CCR
4