LH28F800BVE-TV85 Sharp Electronics, LH28F800BVE-TV85 Datasheet - Page 8

• Manufacturer Part Number: LH28F800BVE-TV85
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVE-TV85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

DQ
RY/BY#
Symbol
BYTE#
A
GND
WE#
WP#
CE#
OE#
V
RP#
0
0
V
A
NC
-A
-DQ
CC
PP
-1
18
15
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY GROUND: Do not float any ground pins.
INPUT/
DRAIN
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
Type
ADDRESS INPUTS: Addresses are internally latched during a write cycle.
A
A
A
A
DATA INPUT/OUTPUTS:
DQ
status register and identifier code read cycles. Data pins float to high-impedance when the chip is
deselected or outputs are disabled. Data is internally latched during a write cycle.
DQ
read cycles in ×16 mode; not used for status register and identifier code read mode. Data pins float
to high-impedance when the chip is deselected, outputs are disabled, or in ×8 mode (Byte#=V
Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
device to read array mode. With RP#=V
blocks without WP# state. Block erase or word/byte write with V
results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WRITE PROTECT: Master control for boot blocks locking. When V
be erased and programmed.
BYTE ENABLE: BYTE# V
and DQ
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
internal operation (block erase or word/byte write). RY/BY#-high Z indicates that the WSM is
ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte
write is suspended, or the device is in deep power-down mode.
BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or
writing words/bytes. With V
word/byte write with an invalid V
not be attempted.
DEVICE POWER SUPPLY: Do not float any power pins. With V
the flash memory are inhibited. Device operations at invalid V
produce spurious results and should not be attempted.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
-1
0
11
15
-A
0
8
-A
-A
-DQ
-DQ
10
14
18
8-15
7
15
: Byte Select Address. Not used in ×16 mode.
: Row Address. Selects 1 of 2048 word lines.
: Column Address. Selects 1 of 16 bit lines.
: Main Block Address. (Boot and Parameter block Addresses are A
:Inputs data and commands during CUI write cycles; outputs data during memory array,
:Inputs data during CUI write cycles in ×16 mode; outputs data during memory array
float. BYTE# V
Table 2. Pin Descriptions
IL
PP
IH
places device in ×8 mode. All data is then input or output on DQ
places the device in ×16 mode , and turns off the A
V
PP
PPLK
(see DC Characteristics) produce spurious results and should
, memory contents cannot be altered. Block erase and
Name and Function
HH
, block erase or word/byte write can operate to all
CC
IH
voltage (see DC Characteristics)
CC
<RP#<V
IL
V
, locked boot blocks cannot
LKO
HH
, all write attempts to
12
-A
produce spurious
18
-1
.)
input buffer.
Rev. 1.2
IL
0-7
).
,