LH28F800BVE-TV85 Sharp Electronics, LH28F800BVE-TV85 Datasheet - Page 23

• Manufacturer Part Number: LH28F800BVE-TV85
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVE-TV85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

5.5 V
Block erase and word/byte write are not guaranteed if V
falls outside of a valid V
a valid 4.5V-5.5V range, or RP# V
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to V
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V
the status register.
The CUI latches commands issued by system software and
is not altered by V
Its state is read array mode upon power-up, after exit from
deep power-down or after V
After block erase or word/byte write, even after V
transitions down to V
array mode via the Read Array command if subsequent
access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure or word/byte writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (V
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
CC
, V
PP
, RP# Transitions
PP
PPLK
IL
or CE# transitions or WSM actions.
PPH1/2
during block erase or word/byte
, the CUI must be placed in read
CC
transitions below V
range, V
IH
or V
CC
HH
falls outside of
. If V
PP
or V
LKO
PP
IL
error
clear
.
CC
PP
PP
)
A system designer must guard against spurious writes for
V
WE# and CE# must be low for a command write, driving
either to V
command sequence architecture provides added level of
protection against data alteration.
WP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=V
regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to V
access is again needed, the devices can be read following
the t
first raised to V
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
CC
PHQV
voltages above V
and t
IH
PHWL
will inhibit writes. The CUI’s two-step
IH
. See AC Characteristics− Read Only
wake-up cycles required after RP# is
LKO
when V
IL
standby or sleep modes. If
PP
is active. Since both
Rev. 1.2
IL