TE28F160S3100 Intel, TE28F160S3100 Datasheet - Page 6

• Manufacturer Part Number: TE28F160S3100
• Manufacturer: Intel

Specifications of TE28F160S3100

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S3, 28F320S3
The device incorporates two Write Buffers of 32
bytes (16 words) to allow optimum-performance
data programming. This feature can improve
system program performance by up to four times
over non-buffer programming.
Individual block locking uses a combination of block
lock-bits to lock and unlock blocks. Block lock-bits
gate block erase, full chip erase, program and write
to
operations (Set Block Lock-Bit and Clear Block
Lock-Bits commands) set and clear lock-bits.
The Status Register and the STS pin in RY/BY#
mode indicate whether or not the device is busy
executing an operation or ready for a new
command. Polling the Status Register, system
software retrieves WSM feedback. STS in RY/BY#
mode gives an additional indicator of WSM activity
by providing a hardware status signal. Like the
Status Register, RY/BY#-low indicates that the
WSM is performing a block erase, program, or lock-
bit operation. RY/BY#-high indicates that the WSM
is ready for a new command, block erase is
suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
6
buffer
16-Mbit: A
32-Mbit: A
operations.
0
0 -
- A
A
20
21
Input Buffer
Address
Address
Counter
Latch
Lock-bit
Y-Decoder
X-Decoder
configuration
Figure 1. Block Diagram
Output Buffer
Comparator
16-Mbit: Thirty-two
32-Mbit: Sixty-four
Identifier
Register
Register
DQ
64-Kbyte Blocks
Status
Query
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode with address A
byte and high byte. BYTE# at logic high enables
16-bit operation with address A
lowest order address. Address A
bit mode.
When one of the CE
pins are at V
standby mode. Driving RP# to GND enables a deep
power-down mode which significantly reduces
power consumption, provides write protection,
resets the device, and clears the Status Register. A
reset time (t
high until outputs are valid. Likewise, the device
has a wake time (t
to the CUI are recognized.
1.3
The 16-Mbit device is available in the 56-lead
TSOP, 56-lead SSOP and
32- Mb device is available in the 56-lead SSOP and
µBGA packages. The pinouts are shown in Figures
2, 3 and 4.
Data
0
Y-Gating
- DQ
15
ADVANCE INFORMATION
Input Buffer
Pinout and Pin Description
Multiplexer
PHQV
CC
, the component enters a CMOS
) is required from RP# switching
PHEL
X
# pins (CE
0
Write State
) from RP#-high until writes
Machine
Command
selecting between the low
Interface
User
BGA packages. The
0
0
#, CE
is not used in 16-
Program/Erase
Voltage Switch
1
I/O Logic
becoming the
1
#) and RP#
STS
WE#
WP#
CE#
OE#
RP#
V
BYTE#
V
GND
V
CC
PP
CC