TE28F160S3100 Intel, TE28F160S3100 Datasheet
TE28F160S3100
Specifications of TE28F160S3100
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TE28F160S3100 Summary of contents
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... GND, selective block locking, and program/erase lockout during power transitions. These PP alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel’s 0.4 m ETOX™ V process technology. It comes in the industry-standard 56-lead SSOP and BGA packages. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... Block Status Register ..........................20 4.2.4 CFI Query Identification String.............21 4.2.5 System Interface Information...............22 4.2.6 Device Geometry Definition .................23 4.2.7 Intel-Specific Extended Query Table ...24 4.3 Read Identifier Codes Command ...............25 4.4 Read Status Register Command................25 4.5 Clear Status Register Command................26 4.6 Block Erase Command ..............................26 4 ...
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REVISION HISTORY Number -001 Original version 4 Description ADVANCE INFORMATION ...
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... Section 6 covers electrical specifications for extended temperature product offerings. 1.1 New Features The Word-Wide FlashFile memory family maintains basic compatibility with Intel’s 28F016SA and 28F016SV. Key enhancements include: Common Flash Interface (CFI) Support Scaleable Command Set (SCS) Support Low Voltage Technology ...
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The device incorporates two Write Buffers of 32 bytes (16 words) to allow optimum-performance data programming. This feature can improve system program performance four times over non-buffer programming. Individual block locking uses a combination of ...
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Table 1. Pin Descriptions Sym Type A –A INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally 0 21 latched during a write cycle x16 mode not used; input buffer is off. 0 ...
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Figure 3. SSOP 56-Lead Pinout ADVANCE INFORMATION 28F160S3, 28F320S3 9 ...
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... Figures are not drawn to scale. 2. Address A is not included in the 28F160S3 More information on µBGA* packages is available by contacting your Intel/Distribution sales office. Figure 4. BGA* Package Pinout 2.0 PRINCIPLES OF OPERATION The word-wide memories include an on-chip Write State Machine (WSM) to manage block erase, program, ...
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... Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location. ADVANCE INFORMATION 2.1 Data Protection Depending on the application, the system ...
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... RESET# signal that resets the system CPU. 3.5 Read Query Operation The read query operation outputs block status, – Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information. ADVANCE INFORMATION . Time t is required PHQV corrupted after is required after ...
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Read Identifier Codes Operation The read-identifier codes operation outputs the manufacturer code, device code, and block lock configuration codes for each block configuration (see Figure 6). Using the manufacturer and device codes, the system software automatically match the device ...
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Mode Notes RP Read 1 Output Disable Standby Reset/Power Down Mode Read Identifier 4 V ...
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... Table 3. Word-Wide FlashFile™ Memory Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd Set (14) Read Array SCS/BCS 1 Read Identifier Codes SCS/BCS 2 Read Query SCS 2 Read Status Register SCS/BCS 2 Clear Status Register SCS/BCS 1 Write to Buffer SCS > 2 Word/Byte Program SCS/BCS ...
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... Commands other than those shown above are reserved for future use and should not be used. 14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set. ...
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... Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI ...
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Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Word Addressing Location x16 device/ 10h x16 mode 11h 12h x16 device/ N/A (1) x8 mode NOTE: 1. The system must drive ...
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... Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. ADVANCE INFORMATION 28F160S3, 28F320S3 ...
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... BLOCK STATUS REGISTER The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 7. Block Status Register Offset Length (bytes) (BA+2)h (1) 01h Block Status Register BSR.0 = Block Lock Status ...
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... CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the specification and which vendor-specified command set(s) supported. Table 8. CFI Identification Offset Length (Bytes) 10h 03h Query-Unique ASCII string “QRY“ ...
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SYSTEM INTERFACE INFORMATION The following device information can be useful in optimizing system interface software. Table 9. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum Program/Erase Voltage CC bits 7–4 BCD volts bits ...
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... DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset Length (bytes) 27h 01h Device Size = 2 N 28h 02h Flash Device Interface Description value 0002h 2Ah 02h Maximum Number of Bytes in Write Buffer = 2 2Ch ...
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... INTEL-SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 11. Primary-Vendor Specific Extended Query Offset (1) Length (bytes) (P)h 03h Primary Extended Query Table Unique ASCII String “PRI“ ...
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Table 11. Primary-Vendor Specific Extended Query (Continued) Offset Length (bytes) (P+C)h 01h V Logic Supply Optimum Program/Erase voltage (highest CC performance) bits 7–4 bits 3–0 (P+D)h 01h V [Programming] Supply Optimum Program/Erase voltage PP bits 7–4 bits 3–0 reserved Reserved ...
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Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ and DQ are invalid. When the ...
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... After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM to begin copying the buffer data to the flash memory command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and Status Register bits SR.5 and SR.4 will be set to “ ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program ...
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... WSM is busy. configuration 01 ER INT, pulse mode ---- -used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases. Helpful for reformatting blocks after file system free space reclamation or ‘cleanup’ ...
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Table 15. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block erase suspended 0 = Block erase in progress/completed SR.5 ...
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... Count register. 2. The device now outputs the Status Register when read (XSR is no longer available). 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for Yes maximum programming performance. ...
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Figure 8. Single Byte/Word Program Flowchart ADVANCE INFORMATION 28F160S3, 28F320S3 33 ...
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Figure 9. Program Suspend/Resume Flowchart 34 ADVANCE INFORMATION ...
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... Another Issue Read Block Status Command Erase? No Read Status Register 0 SR Full Status Check if Desired Erase Flash Block(s) Complete Figure 10. Block Erase Flowchart ADVANCE INFORMATION 28F160S3, 28F320S3 Bus Command Operation Write Erase Block Data = 28h or 20h Addr = Block Address Read XSR.7=valid ...
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Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Write Read or Write? Write Read Array No Data Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error 0 ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections ( OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CEx# while OE# should be connected to all memory devices and the system’ ...
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... Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” ...
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CAPACITANCE Table 18. Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 1.35 0.0 AC test inputs are driven at 2.7V for a Logic ...
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DC CHARACTERISTICS Table 19. DC Characteristics, T Sym Parameter Notes I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current ...
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... PPLK PPH1 5. Automatic Power Savings (APS) reduces typical I 6. CMOS inputs are either V ± 0.2V or GND ± 0.2V. TTL inputs are either Sampled, not 100% tested. 8. With V V flash memory writes are inhibited. CC LKO ADVANCE INFORMATION 28F160S3, 28F320S3 Min Max Unit 7 -0 ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Table 20. AC Read Characteristics Versions (4) 3.3V ± 0.3V V (All units in ns unless otherwise noted) 2. Sym Parameter R1 t Read/Write Cycle Time AVAV R2 ...
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Note the latter and CE # low or the first Figure 17. AC Waveform for Read Operations ADVANCE INFORMATION 28F160S3, 28F320S3 # high ...
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AC CHARACTERISTICS - WRITE OPERATIONS Table 21. Write Operations Versions (5) # Sym Parameter RP# High Recovery to WE# (CE ) PHWL PHEL Setup to WE# Going Low ELWL ...
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NOTES power-up and standby Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read Status Register data. F. Write Read Array command. ...
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RESET OPERATIONS Figure 19. AC Waveform for Reset Operation Table 22. Reset AC Specifications # Sym Parameter P1 t RP# Pulse Low Time PLPH (If RP# is tied this specification is CC not applicable) ...
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ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE Table 23. Erase/Write/Lock Performance Version # Sym Parameter Byte/word program time W16 (using write buffer) t Per byte program time WHQV1 W16 (without write buffer) t EHQV1 t Per word program time WHQV1 ...
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Table 24. Erase/Write/Lock Performance Version # Sym Parameter Byte/word program time W16 (using write buffer) t Per byte program time WHQV1 W16 t (without write buffer) EHQV1 t Per word program time WHQV1 W16 t (without write buffer) ...
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... APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION Product line designator for all Intel Flash products Package DT = Extended Temp. 56-Lead SSOP TE = Extended Temp. 56-Lead TSOP GT = Extended Temp. µ 56-Bump BGA* package Device Density 160 = 16-Mbit 320 = 32-Mbit Order Code by Density 56-lead TSOP S3-100 ...
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... CFI - Common Flash Interface Reference Code Sales Office NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...