LMX2332LTM National Semiconductor, LMX2332LTM Datasheet - Page 17

• Manufacturer Part Number: LMX2332LTM
• Description: 83F3835
• Manufacturer: National Semiconductor

Specifications of LMX2332LTM

• Pll Type: Frequency Synthesis
• Frequency: 1.1GHz
• Supply Current: 3mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: No

X = don't care condition
Note 12: When the F
Note 13: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 14: The Fastlock mode utilizes the F
occurs whenever the RF loop's lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
Note 15: The IF Counter Reset mode resets IF PLL's R and N counters and brings IF charge pump output to a TRI-STATE condition. The RF Counter Reset
mode resets RF PLL's R and N counters and brings RF charge pump output to a TRI-STATE condition. The IF and RF Counter Reset mode resets all counters
and brings both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits then N counter resumes counting in “close” alignment with the
R counter. (The maximum error is one prescaler cycle.)
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronously powerdown
occurs if the respective loop's R18 bit (Do TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous powerdown
occurs if the loop's R18 bit is HI when its N20 bit becomes HI.
In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency jumps.
Once the powerdown program bit N20 is loaded, the part will go into powerdown mode when the charge pump reaches a TRI-
STATE condition.
In the asynchronous powerdown mode, the device powers down immediately after the LE pin latches in a HI condition on the
powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces the respective
loop's R and N dividers to their load state condition and debiasing of its respective f
circuitry function does not become disabled until both IF and RF powerdown bits are activated. The MICROWIRE control register
remains active and capable of loading and latching data during all of the powerdown modes.
The device returns to an actively powered up condition in either synchronous or asynchronous modes immediately upon LE latching
LOW data into bit N20.
RF R[19]
(RF LD)
X
X
X
X
0
0
1
1
0
0
1
1
o
LD output is disabled, it is actively pulled to a low logic state.
IF R[19]
(IF LD)
0
1
0
1
0
0
1
1
0
1
0
1
o
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
R18
12806 Version 9 Revision 2
0
1
0
1
TABLE 3. The F
N20
0
0
1
1
RF R[20]
(RF F
Powerdown Mode Select Table
0
0
0
0
0
1
0
1
1
1
1
1
PLL Active
PLL Active
(Charge Pump Output TRI-STATE)
Synchronous Powerdown Initiated
Asynchronous Powerdown Initiated
o
)
o
LD (Pin 10) Output Truth Table
Print Date/Time: 2011/07/11 15:54:42
Powerdown Status
17
IF R[20]
(IF F
0
0
0
0
1
0
1
0
1
1
1
1
o
)
IN
Disabled
IF Lock Detect
RF Lock Detect
RF/IF Lock Detect
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
Fastlock
IF Counter Reset
RF Counter Reset
IF and RF Counter Reset
input to a high impedance state. The oscillator
(Note
(Note
F
(Note
14)
o
12)
(Note
Output State
(Note
(Note
(Note
13)
13)
15)
13)
15)
(Note
15)
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