XRP7740ILB-0X18-F Exar Corporation, XRP7740ILB-0X18-F Datasheet - Page 6

• Manufacturer Part Number: XRP7740ILB-0X18-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7740ILB-0X18-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 6.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1697

PIN ASSIGNMENT
PIN DESCRIPTION
© 2011 Exar Corporation
PGND1- PGND4
Name
AVDD
VCCD
VCCA
VIN1
VIN2
GPIO4_SDA
GPIO5_SCL
Pin Number
36,31,16,21
ENABLE
GPIO0
GPIO1
GPIO2
GPIO3
DGND
DVDD
AVDD
39
38
37
26
1
10
1
2
3
4
5
6
7
8
9
Power source for the internal linear regulators to generate VCCA, VDD and the Standby
LDO (LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in
UVLO1 fault generation – if VIN1 falls below the user programmed limit, all channels are
shut down. The VIN1 pin needs to be tied to VIN2 on the board with a short trace.
If the Vin2 pin voltage falls below the user programmed UVLO VIN2 level all channels are
shut down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace.
Output of the internal 5V LDO. This voltage is internally used to power analog blocks. This
pin should be bypassed with a minimum of 4.7uF to AGND
Gate Drive input voltage. This is not an output voltage. This pin can be connected to
VCCA to provide power for the Gate Drive. VCCD should be connected to VCCA with the
shortest possible trace and decouple with a minimum 1µF capacitor. Alternatively, VCCD
could be connected to an external supply (not greater than 5V).
Power Ground. Ground connection for the low side gate driver. Connect at low side FET
source.
Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD
and AGND close to the chip (with short traces).
Q
Q
u
u
Fig. 3: XRP7708/40 Pin Assignment
a
a
d
d
C
C
h
h
a
a
Exposed Pad: AGND
6mm X 6mm
n
n
XRP7708
XRP7740
n
6/28
n
TQFN
e
e
l
l
D
D
i
i
g
g
i
i
t
t
Description
a
a
l
l
P
P
X
X
W
W
R
R
M
M
P
P
S
S
7
7
t
t
7
7
e
e
0
0
p
p
30
29
28
27
26
25
24
23
22
21
8
8
D
D
o
o
a
a
GL2
LX2
GH2
BST2
VCCD
BST4
GH4
LX4
GL4
PGND4
w
w
n
n
n
d
n
d
C
C
X
X
o
o
R
R
n
n
P
P
t
t
Rev. 1.2.0
r
r
7
7
o
o
7
7
l
l
l
l
e
e
4
4
r
r
0
0
s
s