XRP7740ILB-0X18-F Exar Corporation, XRP7740ILB-0X18-F Datasheet - Page 23

• Manufacturer Part Number: XRP7740ILB-0X18-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7740ILB-0X18-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 6.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1697

The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows
any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to
set the polarity of GPIO 0 though 5. If the IC operates in I
[5:4] are ignored.
Each GPIO can be configured to enable a specific power rail for the system.
register allows a GPIO to enable/disable any of the following rails controlled by the chip:
When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they
will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be
controlled through the I
The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is
asserted when all rails configured for this specific IO are within specified limits for regulation. This
information can also be found in the READ_PWRGD_SS_FLAG status register.
The GPIOs can be configured to signal Fault or Warning conditions when they occur in the chip.
Each GPIO can be configured to signal one of the following:
I
The I
This interface allows for the full control, monitoring, and reconfiguration of the semiconductor.
Each device in an I
always has to be sent as the first byte after the start condition in the I
There is one address byte required since 7-bit addresses are used. The last bit of the address byte
is the read/write-bit and should always be set according to the required operation. This 7-bit I
address is stored in the NVM. One can program a blank device with the 7-bit Slave address or
select one of the preprogrammed options. The 7-bit address plus the R/W bit create an 8-bit data
value that is sent on the bus.
© 2011 Exar Corporation
2
GPIO Pins Polarity
Supply Rail Enable
Power Good Indicator
Fault and Warning Indication
C C
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OMMUNICATION
C communication is standard 2-wire communication available between the Host and the IC.
A single buck power controller
The Standby LDO
Any mix of the Standby LDO and power controller(s)
OCP Fault on Channel 1 - 4
OCP Warning on Channel 1 - 4
OVP Fault on Channel 1 - 4
UVLO Fault on VIN1 or VIN2
UVLO Warning on VIN1 or VIN2
Over Temperature Fault or Warning
2
C-bus system is activated by sending a valid address to the device. The address
2
C interface.
MSB
6
Fig. 29: Alignment of I2C address in 8 bit byte
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LSB
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R
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M
R/W
P
P
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7
2
C -bus protocol
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