MT48LC4M16A2P-75:GTR Micron Technology Inc, MT48LC4M16A2P-75:GTR Datasheet - Page 60

• Manufacturer Part Number: MT48LC4M16A2P-75:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC4M16A2P-75:GTR

• Lead Free Status / Rohs Status: Compliant

Figure 43:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMU
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CKE
A10
CLK
DQ
t CKS
t CMS
Single READ – With Auto Precharge
t AS
t AS
t AS
ACTIVE
ROW
ROW
T0
BANK
t CMH
t CKH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and CL = 2.
2. READ command not allowed or
3. x16: A8, A9 and A11 = “Don’t Care”
NOP
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CL
T2
NOP 2
t CH
T3
NOP 2
ENABLE AUTO PRECHARGE
t CMS
60
COLUMN m 3
BANK
T4
READ
t
RAS would be violated.
t CMH
CAS Latency
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
t RP
D
T6
OUT
NOP
64Mb: x4, x8, x16 SDRAM
t OH
m
t HZ
©2000 Micron Technology, Inc. All rights reserved.
ACTIVE
BANK
ROW
T7
ROW
Timing Diagrams
T8
NOP
DON’T CARE
UNDEFINED