MT48LC4M16A2P-75:GTR Micron Technology Inc, MT48LC4M16A2P-75:GTR Datasheet - Page 17

• Manufacturer Part Number: MT48LC4M16A2P-75:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC4M16A2P-75:GTR

• Lead Free Status / Rohs Status: Compliant

Figure 7:
Table 6:
Operating Mode
Write Burst Mode
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
CAS Latency
CAS Latency
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
COMMAND
COMMAND
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M0–M2 applies to both read and write
bursts; when M9 = 1, the programmed burst length applies to read bursts, but write
accesses are single-location (nonburst) accesses.
CLK
CLK
DQ
DQ
Speed
-7E
-75
-6
READ
READ
T0
T0
CL = 2
NOP
NOP
T1
T1
t
t AC
LZ
17
CL = 3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
Allowable Operating Frequency (MHz)
T2
NOP
t
t AC
D
LZ
t OH
CL = 2
OUT
≤133
≤100
–
T3
T3
NOP
D
t OH
OUT
64Mb: x4, x8, x16 SDRAM
DON’T CARE
UNDEFINED
Functional Description
©2000 Micron Technology, Inc. All rights reserved.
T4
CL = 3
≤166
≤143
≤133