MT48LC4M16A2P-75:GTR Micron Technology Inc, MT48LC4M16A2P-75:GTR Datasheet - Page 51

• Manufacturer Part Number: MT48LC4M16A2P-75:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC4M16A2P-75:GTR

• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
22. V
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and
33. CKE is HIGH during refresh command period
34. The -6 speed grade does not support CL = 2.
cannot be greater than one-third of the cycle rate. V
a pulse width ≤ 3ns.
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
7ns after the first clock delay, after the last WRITE is executed.
t
t
limit is actually a nominal value and does not result in a fail value.
AC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
CK = 6ns.
IH
overshoot: V
IH
(MAX) = V
t
CK = 7.5ns; for -7E, CL = 2 and
51
DD
Q + 2V for a pulse width ≤ 3ns, and the pulse width
t
WR, and PRECHARGE commands). CKE may be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC (MIN) else CKE is LOW. The I
t
CK = 7.5ns; for -6, CL = 3 and
IL
64Mb: x4, x8, x16 SDRAM
undershoot: V
t
RP) begins 6ns/7ns/7.5ns/
©2000 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
Notes
DD
6