MT48LC2M32B2P-7:GTR Micron Technology Inc, MT48LC2M32B2P-7:GTR Datasheet - Page 60

• Manufacturer Part Number: MT48LC2M32B2P-7:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC2M32B2P-7:GTR

• Lead Free Status / Rohs Status: Compliant

Figure 42:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
COMMAND
BA0, BA1
DQM 0-3
A0-A9
CKE
A10
CLK
DQ
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
BANK
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
READ – Full-Page Burst
t RCD
Notes:
t CL
T1
NOP
t CH
1. For this example, CL = 2.
2. A8 and A9 = “Don’t Care.”
3. Page left open; no
t CMS
t CK
COLUMN m 2
T2
BANK
READ
t CMH
CAS Latency
T3
NOP
t LZ
t AC
t
RP.
T4
Dout m
NOP
t OH
t AC
60
256 locations within same row
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
D
T5
OUT
NOP
t OH
m+1
Full page completed
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t AC
D
T6
OUT
NOP
t OH
t AC
m+2
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
(
(
(
(
)
(
)
(
)
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
)
(
)
(
)
)
)
)
Tn + 1
D
NOP
OUT
t OH
m-1
t AC
©2001 Micron Technology, Inc. All rights reserved.
BURST TERM
64Mb: x32 SDRAM
Tn + 2
3
D
Timing Diagrams
OUT
t OH
m
t AC
Tn + 3
D
OUT
NOP
DON’T CARE
UNDEFINED
t OH
m+1
t HZ
Tn + 4
NOP