MT48LC2M32B2P-7:GTR Micron Technology Inc, MT48LC2M32B2P-7:GTR Datasheet - Page 53
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MT48LC2M32B2P-7:GTR
Manufacturer Part Number
MT48LC2M32B2P-7:GTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC2M32B2P-7GTR.pdf
(69 pages)
Specifications of MT48LC2M32B2P-7:GTR
Lead Free Status / Rohs Status
Compliant
- Current page: 53 of 69
- Download datasheet (3Mb)
Figure 35:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
COMMAND
DQM0–3
BA0, BA1
A0–A9
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
COLUMN m
READ
T0
BANK
t CMH
Clock Suspend Mode
t CKH
t AH
t AH
t AH
2
Notes:
t CMS
t CK
T1
NOP
t CMH
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. A8 and A9 = “Don’t Care.”
t CL
t CKS t CKH
T2
NOP
t LZ
t CH
t AC
T3
D
OUT
m
T4
NOP
t OH
53
t AC
D
T5
OUT
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
m + 1
t HZ
T6
NOP
COLUMN e
t DS
BANK
D
WRITE
T7
OUT
t DH
e
2
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Timing Diagrams
T8
D
DON’T CARE
UNDEFINED
OUT
T9
NOP
e + 1
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