MT48LC2M32B2P-7:GTR Micron Technology Inc, MT48LC2M32B2P-7:GTR Datasheet - Page 34

• Manufacturer Part Number: MT48LC2M32B2P-7:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC2M32B2P-7:GTR

• Lead Free Status / Rohs Status: Compliant

Figure 23:
Figure 24:
Clock Suspend
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
PRECHARGE Command
Power-Down
A0–A9
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended (see
examples in Figures 25 and 26 on page 35).
CKE
BA0, 1
CLK
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
All banks idle
Enter power-down mode.
HIGH
t CKS
NOP
Bank Selected
All Banks
ADDRESS
Input buffers gated off
BANK
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DON’T CARE
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Exit power-down mode.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
> t CKS
NOP
DON’T CARE
©2001 Micron Technology, Inc. All rights reserved.
ACTIVE
64Mb: x32 SDRAM
t RCD
t RAS
t RC
Commands