AFBR-79E4Z-D Avago Technologies US Inc., AFBR-79E4Z-D Datasheet - Page 18

• Manufacturer Part Number: AFBR-79E4Z-D
• Description: 56T4987
• Manufacturer: Avago Technologies US Inc.

Specifications of AFBR-79E4Z-D

• Applications: Gigabit Ethernet
• Data Rate Max: 10.3125Gbps
• Supply Voltage: 3.3V
• Wavelength Typ: 850nm
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I/O Timing for Control and Status Functions
The following characteristics are defi ned over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
18
Parameter
Initialization Time
LPMode Assert Time
Interrupt Assert Time
Interrupt De-assert Time
Reset Init Assert Time
Reset Assert Time
Serial Bus Hardware
Ready Time
Monitor Data Ready Time
RX LOS Assert Time
TX Fault Assert Time
Flag Assert Time
Mask Assert Time
Mask Deassert TIme
Power Set Assert Time
Power Set Deassert Time
RX Squelch Assert Time
RX Squelch Deassert Time
TX Squelch Assert Time
TX Squelch Deassert Time
TX Disable Assert Time
TX Disable Deassert Time
RX Output Disable
Assert Time
RX Output Disable Deassert
Time
Squelch Disable Assert Time
Squelch Disable Deassert Time toff _sqdis
Symbol
t_init
ton_LPMode
ton_IntL
Toff _IntL
t_reset_init
t_reset
t_serial
t_data
ton_los
ton_Txfault
ton_Flag
ton_Mask
toff _Mask
ton_Pdown
toff _Pdown
ton_Rxsq
toff _Rxsq
ton_Txsq
toff _Txsq
ton_txdis
toff _txdis
ton_rxdis
toff _rxdis
ton_sqdis
Min
Typ
Max
2000
100
200
500
2
2000
2000
2000
100
200
200
100
100
100
300
80
80
400
400
100
400
100
100
100
100
Units Reference
ms
s
ms
s
s
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
s
s
ms
ms
ms
ms
ms
ms
ms
ms
Time from power on, hot plug or rising edge of Reset until the
module is fully functional. This time does not apply to non Power
level 0 modules in the Low Power state
Time from assertion of LPMode until the module power
consumption enters power level 1
Time from occurrence of condition triggering IntL until
Vout:IntL=Vol
Time from clear on read operation of associated fl ag until
Vout:IntL=Voh. This includes deassert times for RX LOS, TX Fault
and other fl ag bits
A Reset is generated by a low level longer than the minimum reset
pulse time present on the ResetL pin
Time from rising edge on the ResetL pin until the module is fully
functional
Time from power on until module responds to data transmission
over the 2-wire serial bus
Time from power on to data not ready, bit 0 of Byte 2, deasserted
and IntL asserted
Time from RX LOS state to RX LOS bit set and IntL asserted
Time from TX Fault state to TX fault bit set and IntL asserted
Time from occurrence of condition triggering fl ag to associated
fl ag bit set and IntL asserted.
Time from mask bit set until associated IntL assertion is inhibited
Time from mask bit cleared until associated IntL operation resumes
Time from P_Down bit set until module power consumption
enters power level 1
Time from P_Down bit cleared until the module is fully functional
Time from loss of RX input signal until the squelched output
condition is reached
Time from resumption of RX input signals until normal RX output
condition is reached
Time from loss of TX input signal until the squelched output
condition is reached
Time from resumption of TX input signals until normal TX output
condition is reached
Time from TX Disable bit set until optical output falls below 10%
of nominal
Time from TX Disable bit cleared until optical output rises above
90% of nominal
Time from RX Output Disable bit set until RX output falls below
10% of nominal
Time from RX Output Disable bit cleared until RX output rises
above 90% of nominal
This applies to RX and TX Squelch and is the time from bit set until
squelch functionality is disabled
This applies to RX and TX Squelch and is the time from bit cleared
until squelch functionality is enabled