M25PE16-VMW6G Micron Technology Inc, M25PE16-VMW6G Datasheet - Page 15

• Manufacturer Part Number: M25PE16-VMW6G
• Manufacturer: Micron Technology Inc

Specifications of M25PE16-VMW6G

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

M25PE16
4.8.2
Specific hardware and software protections
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be hardware protected with the help of the W
input pin.
SPM1 and SPM2
Table 2.
Sector lock register
down bit
Lock
The first software protected mode (SPM1) is managed by specific lock registers
assigned to each 64 Kbyte sector.
The lock registers can be read and written using the read lock register (RDLR) and
write to lock register (WRLR) instructions.
In each lock register two bits control the protection of each sector: the write lock bit and
the lock down bit.
–
–
The write lock bit and the lock down bit are volatile and their value is reset to ‘0’ after a
power-down or a reset (see
The definition of the lock register bits is given in
0
0
1
1
Write lock bit:
The write lock bit determines whether the contents of the sector can be modified
(using the write, program or erase instructions). When the write lock bit is set to ‘1’,
the sector is write protected – any operations that attempt to change the data in
the sector will fail. When the write lock bit is reset to ‘0’, the sector is not write
protected by the lock register, and may be modified.
Lock down bit:
The lock down bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the lock down bit is set to ‘1’, further
modification to the write lock and lock down bits cannot be performed. A reset, or
power-up, is required before changes to these bits can be made. When the lock
down bit is reset to ‘0’, the write lock and lock down bits can be changed.
Software protection truth table (sectors 0 to 31, 64-Kbyte granularity)
lock bit
Write
0
1
0
1
Sector unprotected from program/erase/write operations, protection status
reversible
Sector protected from program/erase/write operations, protection status
reversible
Sector unprotected from program/erase/write operations,
sector protection status cannot be changed except by a reset or power-up.
Sector protected from program/erase/write operations,
Sector protection status cannot be changed except by a reset or power-up.
Table 12: Device status after a Reset Low
Protection status
Table 9: Lock register
Operating features
out.
pulse).
15/58