HBLXT9785HE.C2 Intel, HBLXT9785HE.C2 Datasheet - Page 190
HBLXT9785HE.C2
Manufacturer Part Number
HBLXT9785HE.C2
Description
Manufacturer
Intel
Datasheet
1.HBLXT9785HE.C2.pdf
(221 pages)
Specifications of HBLXT9785HE.C2
Lead Free Status / Rohs Status
Not Compliant
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 81
Figure 62
Table 82
Cortina Systems
Power-Up Timing Parameters
RESET_L Recovery Timing
RESET_L Recovery Timing Parameters
®
Voltage Threshold
Power-up recovery time
Software power-down
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
2. The minimum time required between bringing up consecutive ports powered down by Register bit 0.11, or
Reset pulse width
Reset recovery delay
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
a software or hardware reset.
testing.
Parameter
Parameter
2
MDIO,etc
RESET
tRcdly
t
Sym
Sym
t
SPDR
tPW
PDR
v1
Min
100
Min
2.1
20
0.4
10
Typ1
Typ1
–
–
–
–
–
tPW
Max
–
–
–
Max
–
–
Units
ms
ms
V
Units
ms
ns
tRcdly
6.0 Test Specifications
Test Conditions
Test Conditions
–
–
–
–
–
Page 190
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