HBLXT9785HE.C2 Intel, HBLXT9785HE.C2 Datasheet - Page 179

• Manufacturer Part Number: HBLXT9785HE.C2
• Manufacturer: Intel

Specifications of HBLXT9785HE.C2

• Lead Free Status / Rohs Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 45
Table 67
Cortina Systems
SS-SMII - 100BASE-TX Receive Timing
SS-SMII - 100BASE-TX Receive Timing Parameters
®
REFCLK rising edge to RxCLK
rising edge
RxData/RxSYNC output delay
from RxCLK rising edge
RxData/RxSYNC Rise/Fall time
Receive start of /J/ to CRS
asserted
Receive start of /T/ to CRS
de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
Parameter
REFCLK
RxSYNC
RxData
RxCLK
TPFI
t
Sym
4
t1
t2
t3
t4
t5
t
1
t
2
Min
t
1.5
3
–
–
–
–
t
3
Typ1
1.5
1.0
21
25
–
t
Max
3
27
30
–
5
–
Units
BT
BT
ns
ns
ns
2
2
t
5
6.0 Test Specifications
Minimum C
Maximum C
Test Conditions
–
–
–
–
L
L
Page 179
= 5pF
= 40pF