HBLXT9785HE.C2 Intel, HBLXT9785HE.C2 Datasheet - Page 145

• Manufacturer Part Number: HBLXT9785HE.C2
• Manufacturer: Intel

Specifications of HBLXT9785HE.C2

• Lead Free Status / Rohs Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.9.3.6.2
4.9.3.6.3
4.9.3.7
Note:
4.9.3.7.1
Cortina Systems
The scrambler/descrambler can be bypassed by setting Register bit 16.12 = 1. The
scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is
provided for diagnostic and test support.
Baseline Wander Correction
The LXT9785/LXT9785E provides a baseline wander correction function which makes the
device robust under all network operating conditions. The MLT3 coding scheme used in
100BASE-TX is, by definition, “unbalanced”. This means that the DC average value of the
signal voltage can “wander” significantly over short time intervals (tenths of seconds). This
wander may cause receiver errors, particularly in less robust designs, at long line lengths
(100 meters). The exact characteristics of the wander are completely data dependent.
The LXT9785/LXT9785E baseline wander correction characteristics allow the device to
recover error-free data while receiving worst-case “killer” packets over all cable lengths.
Polarity Correction
The LXT9785/LXT9785E automatically detects and corrects for the condition where the
receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link
pulses or four inverted End-of-Frame (EOF) markers are received consecutively. If link
pulses or data are not received by the maximum receive time-out period, the polarity state
is reset to a non-inverted state. Before the polarity switch occurs, every frame is inverted
and causes RxER to assert. The specific number of RxER events observed depends on
how many link pulses occur between packets.
Fiber PMD Sublayer
The LXT9785/LXT9785E provides an LVPECL interface for connection to an external 3.3
V or 5 V fiber transceiver. (The external transceiver provides the PMD function for the
optical medium.) The LXT9785/LXT9785E uses a 125 Mbaud NRZI format for the fiber
interface, and does not support 10BASE-FL applications.
The BGA15 package does not support fiber interface.
Far End Fault Indications
The LXT9785/LXT9785E Signal Detect pins independently detect signal faults from the
local fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report
Remote Fault indications received from its link partner. The device “ORs” both fault
conditions to set bit 1.4. Register bit 1.4 is set once and clears when read.
The far-end fault detection process in fiber operation requires idles to establish link. Link
will not establish if a far-end fault pattern is the initial signal detected.
Either fault condition causes the LXT9785/LXT9785E to drop the link unless Forced Link
Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status
bits.
In response to locally detected signal faults (SD activated by the local fiber transceiver),
the affected port can transmit the far end fault code if fault code transmission is enabled
by Register bit 16.2.
®
• When Register bit 16.2 = 1, transmission of the far end fault code is enabled. The
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E transmits far end fault code if fault conditions are detected by the
Signal Detect pins.
4.9 100 Mbps Operation
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