LFX125EB-04F256I Lattice, LFX125EB-04F256I Datasheet - Page 60

• Manufacturer Part Number: LFX125EB-04F256I
• Description: IC FPGA 139K GATES 256-BGA
• Manufacturer: Lattice

Specifications of LFX125EB-04F256I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant
• Other names: 220-1238

Lattice Semiconductor
Signal Descriptions
General Purpose
BKy_IOx
GCLK
GSR
NC
GND
V
V
V
V
D
Test and Program/Configuration
TMS
TCK
TDI
TDO
TOE
CFG0
PROGRAMb
DONE
INITb
READ
CCLK
CSb
DATA[0:7]
sysCLOCK PLL
PLL_FBKz
PLL_RSTz
CLK_OUTz
PLL_LOCKz
GND
GND
V
V
sysHSI Block
HSImA_SINP, HSImB_SINP
HSImA_SINN, HSImB_SINN
HSImA_SOUTP, HSImB_SOUTP
HSImA_SOUTN, HSImB_SOUTN
HSImA_SYDT, HSImB_SYDT
HSImA_RECCLK, HSImB_RECCLK
CC
CCJ
CCOy
REFy
CCP0
CCP1
XN,
P0
P1
D
n
2
2
XP
/In
1,2
7
Signal Name
4, 5
3
1
Internal Signal Clock output (routable to any I/O)
Internal Signal Lock output (routable to any I/O)
Internal Signal Symbol alignment detect
Internal Signal Recovered clock
Bi-directional Indicates when configuration is complete
Bi-directional Indicates the device is ready for programming (active low)
Bi-directional sysCONFIG Peripheral Port Data I/O
Signal Type
Input/Output
Output
Output
Output
Output
Input
Input
GND
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
GND
GND
Input
Input
VCC
VCC
VCC
VCC
VCC
—
General purpose I/O number x in I/O Bank y
Global clock/input
Global Set/Reset
No Connect
Ground
Core logic power supply
IEEE 1149.1 TAP power supply
I/O Bank y power supply
I/O Bank y reference voltage
Temperature Sensing Diodes, provide a differential voltage, which
corresponds to the temperature of the device.
Test Mode Select
Test Clock
Test Data In
Test Data Out
Test Output Enable tri-states all I/O pins when driven low
Selects the SRAM memory configuration type (Peripheral or
E
Initiates download from E
memory (active low)
Selects the READ operation when in sysCONFIG mode
sysCONFIG Configuration Clock
sysCONFIG Chip Select (active low)
Optional external feedback
Optional external M divider reset
Left side PLL Ground
Right side PLL Ground
Left side PLL power supply
Right side PLL power supply
P-side of differential serial data input
N-side of differential serial data input
P-side of differential serial data output
N-side of differential serial data output
2
CMOS Refresh)
60
8
2
CMOS or the peripheral port to SRAM
Description
ispXPGA Family Data Sheet