LFX125EB-04F256I Lattice, LFX125EB-04F256I Datasheet - Page 13

• Manufacturer Part Number: LFX125EB-04F256I
• Description: IC FPGA 139K GATES 256-BGA
• Manufacturer: Lattice

Specifications of LFX125EB-04F256I

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant
• Other names: 220-1238

Lattice Semiconductor
Figure 13. EBR Synchronous Read Timing Diagram
Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high, the
write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock
edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the
synchronous write timing.
Figure 14. EBR Synchronous Write Timing Diagram
Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the
read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15
illustrates the asynchronous read timing. For more information about the EBR, refer to Lattice technical note num-
ber TN1028 ispXPGA Memory Usage Guidelines, available at www.latticesemi.com.
Figure 15. EBR Asynchronous Read Timing Diagram
ADDR
ADDR
ADDR
DATA
DATA
DATA
CLK
CLK
WE
WE
WE
CE
OE
OE
ADDR0
t
EBWEDIS
t
EBWEDIS
t
t
EBCES
EBWES
t
EBWES
t
EBADDS
t
EBARAD_H
DATA0
t
EBARADO
Invalid Data
Invalid Data
t
t
EBDATAH
EBCPW
t
t
EBCO
EBPW
WRITE
t
EBDATAS
13
Valid Data
DATA1
t
t
EBADDH
EBADDH
ADDR1
t
t
EBOEDIS
EBOEDIS
WRITE
t
EBADDS
ispXPGA Family Data Sheet
t
t
EBOEEN
EBOEEN
t
EBWEH
t
t
EBWEH
EBCEH
Valid Data
DATA1
t
t
EBWEEN
EBWEEN
ADDR2