LFXP6E-4Q208C Lattice, LFXP6E-4Q208C Datasheet - Page 2
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LFXP6E-4Q208C
Manufacturer Part Number
LFXP6E-4Q208C
Description
IC FPGA 5.8KLUTS 142I/O 208-PQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP6E-4Q208C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number:
LFXP6E-4Q208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
September 2010
Section I. LatticeXP Family Data Sheet
Introduction
Architecture
DC and Switching Characteristics
Features ............................................................................................................................................................. 1-1
Introduction ........................................................................................................................................................ 1-2
Architecture Overview ........................................................................................................................................ 2-1
Clock Distribution Network ................................................................................................................................. 2-6
Dynamic Clock Select (DCS) ........................................................................................................................... 2-11
sysMEM Memory ............................................................................................................................................. 2-11
Programmable I/O Cells (PICs)........................................................................................................................ 2-14
DDR Memory Support...................................................................................................................................... 2-20
sysIO Buffer ..................................................................................................................................................... 2-22
Sleep Mode ...................................................................................................................................................... 2-25
Configuration and Testing ................................................................................................................................ 2-26
Density Shifting ................................................................................................................................................ 2-28
Absolute Maximum Ratings ............................................................................................................................... 3-1
Recommended Operating Conditions ................................................................................................................ 3-1
Hot Socketing Specifications.............................................................................................................................. 3-2
DC Electrical Characteristics.............................................................................................................................. 3-3
Supply Current (Sleep Mode)............................................................................................................................. 3-3
Supply Current (Standby)................................................................................................................................... 3-4
Initialization Supply Current ............................................................................................................................... 3-5
Programming and Erase Flash Supply Current ................................................................................................. 3-6
sysIO Recommended Operating Conditions...................................................................................................... 3-7
PFU and PFF Blocks................................................................................................................................. 2-2
Slice .......................................................................................................................................................... 2-3
Routing...................................................................................................................................................... 2-6
Primary Clock Sources.............................................................................................................................. 2-6
Secondary Clock Sources......................................................................................................................... 2-7
Clock Routing............................................................................................................................................ 2-8
sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-9
sysMEM Memory Block........................................................................................................................... 2-11
Bus Size Matching .................................................................................................................................. 2-12
RAM Initialization and ROM Operation ................................................................................................... 2-12
Memory Cascading ................................................................................................................................. 2-12
Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-12
Memory Core Reset ................................................................................................................................ 2-13
EBR Asynchronous Reset....................................................................................................................... 2-14
PIO .......................................................................................................................................................... 2-16
DLL Calibrated DQS Delay Block ........................................................................................................... 2-20
Polarity Control Logic .............................................................................................................................. 2-22
Hot Socketing.......................................................................................................................................... 2-25
SLEEPN Pin Characteristics ................................................................................................................... 2-26
IEEE 1149.1-Compliant Boundary Scan Testability................................................................................ 2-26
Device Configuration............................................................................................................................... 2-26
Internal Logic Analyzer Capability (ispTRACY)....................................................................................... 2-27
Oscillator ................................................................................................................................................. 2-27
LatticeXP Family Handbook
1
Table of Contents
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