LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 362

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
As shown in Figure 18-1, input to PLL is CLK (133MHz for DDR NP). The PLL generates pll_mclk (133MHz) and
pll_nclk (266MHz). The clocks ddr_clk and ddr_clk_n go to DDR memory and are delayed by I/O pad delay
with respect to pll_mclk. The clocks pll_mclk and pll_nclk are internal to the FPGA. Command and
address signals are clocked by a negative edge of pll_mclk. The signal dqs_out acts as a clock for DDR write
and is generated by negative edge of pll_nclk. The signal ddr_dq_out is the DDR write data bus and gener-
ated by positive edge of pll_nclk. The flops ddr_dq_* latch the read data and are clocked by positive edge of
pll_nclk.
Read Operation
Figure 18-2 shows the timing of the DDR read operation. Table 18-1 describes the timing arcs of the read opera-
tion.
Figure 18-2. Read Timing Diagram
flops (max case)
flops (min case)
(inside FPGA)
At DDR Interface
DQ at FPGA
DQ at FPGA
(max case )
DQ at DDR
DQ at DDR
(min case)
pll_mclk
Inside FPGA
ddr_clk
t
BDD
t
AC
+ t
(min )
PD
t
AC
(max)
t
BDD
18-2
+ t
PD
t
SKEW
for the DDR SDRAM Controller IP Core
t
BDD
Board Timing Guidelines
t
SKEW
t
+ t
AC
PD
(min )
t
AC
(max )
t
BDD
+ t
PD