LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 173

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The various ports and their definitions for the Single Port Memory are included in Table 9-1. The table lists the cor-
responding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive.
Table 9-1. EBR-based Single Port Memory Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can easily cascade eight memories. If the memory size specified by the user requires more than eight
EBR blocks, the software automatically generates the additional address decoding logic which is implemented in
the PFU (external to the EBR blocks).
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 9-2.
Table 9-2. Single Port Memory Sizes for 9K Memories for LatticeECP/EC Devices
Table 9-3 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Table 9-3. Single Port RAM Attributes for LatticeECP/EC Devices
DATA_WIDTH
REGMODE
RESETMODE
CSDECODE
WRITEMODE
GSR
Attribute
Clock
ClockEn
Address
Data
Q
WE
Reset
—
Generated Module
Port Name in
Memory Size
Single Port
Data Word Width
Register Mode (Pipelining) NOREG, OUTREG
Selects the Reset type
Chip Select Decode
Read / Write Mode
Global Set Reset
512 x 18
256 x 36
8K x 1
4K x 2
2K x 4
1K x 9
Description
CLK
CE
AD[x:0]
DI[y:0]
DO[y:0]
WE
RST
CS[2:0]
EBR Block Primitive
Port Name in the
Input Data
DI[17:0]
DI[35:0]
1, 2, 4, 9, 18, 36
ASYNC, SYNC
000, 001, 010, 011, 100, 101, 110,
111
NORMAL, WRITETHROUGH, 
READBEFOREWRITE
ENABLED, DISABLED
DI[1:0]
DI[3:0]
DI[8:0]
DI
Values
9-8
Clock
Clock Enable
Address Bus
Data In
Data Out
Write Enable
Reset
Chip Select
Output Data
Description
DO[17:0]
DO[35:0]
LatticeECP/EC and LatticeXP Devices
DO[1:0]
DO[3:0]
DO[8:0]
DO
NORMAL
1
NOREG
ASYNC
000
ENABLED
Default Value
Rising Clock Edge
Active High
—
—
—
Active High
Active High
—
Address [MSB:LSB]
Memory Usage Guide
Active State
AD[11:0]
AD[10:0]
AD[12:0]
AD[9:0]
AD[8:0]
AD[7:0]
User Selectable
IPexpress
Through
YES
YES
YES
YES
YES
NO