LFXP3E-4TN144C Lattice, LFXP3E-4TN144C Datasheet - Page 354

• Manufacturer Part Number: LFXP3E-4TN144C
• Description: IC FPGA 3.1KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The different path measurements were obtained from the Trace report shown in Figure 17-7 as follows:
The full feedback delay includes both FBDEL0 and FBDEL1 (0.42 + 3.38 = 3.80) under Feedback Path, in addition
to any internal PLL delay added after the FB pin. Such a delay is a programmable attribute defined as FB_PDEL.
This programmable value can be set to any of one of 4 values (DEL0, DEL1, DEL2 or DEL3; DEL0 being 0 delay)
in either the HDL file input to synthesis, or in the graphical Editor for Programmable Integrated Circuits (EPIC) soft-
ware tool included with the ispLEVER software.
Therefore, the total feedback delay would be:
Under “Constraint Details” of the report file, the feedback compensation (FBDEL) is shown to be 5.09 ns. Since this
value is different from 3.804, we conclude that a non-zero value of FB_PDEL was applied (5.10 - 3.80 = 1.29 ns).
This value corresponds to FB_PDEL = DEL2 in an OR4E4-2 device.
Now, let's verify the available margin on this CLOCK_TO_OUT preference:
This value matches the one at the top of the report file (“Passed” section). It also matches the final value under
“Constraints Details”.
ispLEVER Controlled Place and Route
Extensive benchmark experiments have been performed in order to determine the most optimum per device
default settings for all PAR options. At times, improved timing results can be obtained on a design by design basis
by trying different variations of the PAR options. This section describes the techniques that can be used within the
ispLEVER graphical user interface (GUI) to improve timing results from Trace on placed and routed designs.
Running Multiple Routing Passes
Improved timing results can be obtained by increasing the number of routing passes during the Routing phase of
PAR.
The PAR options window in Figure 17-8 can be launched by the following steps:
In the example screen shot shown in Figure 17-8, the router will route the design for five routing iterations, or until
all the timing preferences are met, whichever comes first. For example, PAR will stop after the second routing itera-
tion if it hits a timing score of zero on the second routing iteration.
The highest selection in Placement Effort level will result in longer PAR run times but may give better design timing
results. A lower Placement Effort will result in shorter PAR run times but will likely give less than optimal design tim-
ing results.
• DPDEL = Data Path Delay = 3.16 ns. Shown under Physical Path Details-> Data path in the timing report.
• FBDEL0 = Feedback cell delay across PLL = 0.42 ns, which is the first entry value under Feedback Path.
• FBDEL1 = Feedback routing delay from PLL output to PLL FB pin = 3.38 ns, which is the second entry
1. In the Project Navigator Source window, select the target FPGA device.
2. In the Processes window, right-click the Place & Route Design process and select Properties to open the
value under Feedback Path.
dialog box.
FBDEL = FBDEL0 + FBDEL1 + FB_PDEL = 3.80 + FB_PDEL
M = CKOUT - (CPDEL + DPDEL - FBDEL)
= 7.000 - (8.249 + 3.164 - 5.094) = 0.681 ns
17-10
Lattice Semiconductor FPGA
Successful Place and Route