LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 59

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
sysCLOCK PLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v.G 0.30
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
Parameter
4
2
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
LOCK
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
Default Duty Cycle
Elected
f
f
90% to 90%
10% to 10%
Divider ratio = integer
At 90% or 10%
OUT
OUT
3-23
>= 100MHz
< 100MHz
Conditions
3
3
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
0.195
Min.
420
100
0.5
0.5
25
25
25
45
10
—
—
—
—
—
—
—
1
Typ.
250
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+/- 125
+/- 200
+/- 200
Max.
0.05
0.02
420
420
210
840
150
450
55
10
—
—
—
—
—
Units
UIPP
MHz
MHz
MHz
MHz
MHz
ps
ps
ns
µs
ps
ps
ns
ns
ns
ns
UI
%