LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 160
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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www.latticesemi.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
November 2007
For Further Information
A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com.
For further information about interface standards refer to the following web sites:
• LatticeECP/EC sysIO Usage Guide (TN1056)
• LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049)
• Memory Usage Guide for LatticeECP/EC Devices (TN1051)
• LatticeECP/EC DDR Usage Guide (TN1050)
• Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052)
• LatticeECP-DSP sysDSP Usage Guide (TN1057)
• LatticeECP/EC sysCONFIG Usage Guide (TN1053)
• IEEE 1149.1 Boundary Scan Testability in Lattice Devices
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: ww.pcisig.com
LatticeECP/EC Family Data Sheet
6-1
Supplemental Information
Further Info_01.3
Data Sheet
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