LFE3-35EA-8FN672I Lattice, LFE3-35EA-8FN672I Datasheet - Page 109

IC FPGA 33.3K LUTS 310I/O FN672

LFE3-35EA-8FN672I

Manufacturer Part Number
LFE3-35EA-8FN672I
Description
IC FPGA 33.3K LUTS 310I/O FN672
Manufacturer
Lattice
Series
ECP3r

Specifications of LFE3-35EA-8FN672I

Number Of Logic Elements/cells
33000
Number Of Labs/clbs
4125
Total Ram Bits
1358848
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1163
Lattice Semiconductor
Figure 3-24. Power-On-Reset (POR) Timing
Figure 3-25. sysCONFIG Port Timing
PROGRAMN
DONE
DOUT
CCLK
INITN
sysIO
VCC
DI
V
V
1. Time taken from V
2. Device is in a Master Mode (SPI, SPIm).
3. The CFG pins are normally static (hard wired).
CC
CCIO8
CFG[2:0]
/ V
t
ICFG
DONE
CCLK
CCAUX
1
INITN
t
DPPDONE
2
3
t
IODISS
/
t
t
PRGM
PRGMRJ
t
t
VMC
DINIT
CC
, V
CCAUX
t
DPPINIT
t
t
or V
HSCDI
SUSCDI
CCIO8
(t
(t
HMCDI
SUMCDI
, whichever is the last to cross the POR trip point.
t
ICFG
)
)
t
VMC
3-56
Valid
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
t
t
t
SSCH
SSCL
CODO
Wake Up Clocks
t
IOENSS
GOE Release

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