NOII5SC1300A-QDC ON Semiconductor, NOII5SC1300A-QDC Datasheet - Page 5

• Manufacturer Part Number: NOII5SC1300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII5SC1300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Architecture and Operation
This section presents detailed information about the most important sensor blocks
Floor Plan
Figure 2
It consists basically of a pixel array, one X- and two Y-addressing
registers for the readout in X- and Y-direction, column amplifiers
that correct for the fixed pattern noise, an analog multiplexer, and
an analog output amplifier.
Use the left Y-addressing register for readout operation. Use the
right Y-addressing register for reset of pixel rows. In multiple
slope synchronous shutter mode, the right Y-addressing register
resets the whole pixel core with a lowered reset voltage. In rolling
shows the architecture of the IBIS5-1300 image sensor.
addressing
Y-left
Pixel
Column amplifiers
Figure 2. Block Diagram of IBIS5-1300 Image Sensor
X-addressing
Analog multiplexer
Rev. 9 | www.onsemi.com | Page 5 of 34
Pixel core
Imager core
Y-right
addressing
Output
amplifier
curtain shutter mode, use the right Y-addressing register for the
reset pointer in single and double slope operation to reset one
pixel row.
The on-chip sequencer generates most of the signals for the
image core. Some basic signals (such as start/stop integration,
line and frame sync signals) are generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. You must route the analog pixel output to
the analog ADC input on the outside.
ADC
Sequencer
Sensor
System clock
40 MHz
External
connection
Sample
Reset
C
Column output
NOII5SM1300A
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