NOII5SC1300A-QDC ON Semiconductor, NOII5SC1300A-QDC Datasheet - Page 10

• Manufacturer Part Number: NOII5SC1300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII5SC1300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Global Shutter Supply Considerations
The recommended supply voltage settings listed in
used when the sensor is in global shutter mode only.
Table 8. Global Shutter Recommended Supply Settings
Dual Shutter Supply Considerations
If you analyze the supply settings listed in
some fixed column non-uniformities (FPN) when operating in
rolling shutter mode. If a dual shutter mode (both rolling and
global shutter) is required during operation, you must apply the
Table 10. Overview of Bias Signals
VDDH
VDDR_LEFT
VDDC
VDDA
VDDD
GNDA
GNDD
GND_AB
DEC_CMD
DAC_VHIGH
DAC_VLOW
AMP_CMD
COL_CMD
PC_CMD
ADC_CMD
ADC_VHIGH
ADC_VLOW
Parameter
Signal
Voltage on HOLD switches.
Highest reset voltage.
Pixel core voltage.
Analog supply voltage of the
image core.
Digital supply voltage of the
image core.
Analog ground.
Digital ground.
Anti-blooming ground.
Connect to VDDA with R = 51 k and decouple to GNDA with C = 100 nF. Decoder stage.
Connect to VDDA with R = 0.
Connect to GNDA with R = 0.
Connect to VDDA with R = 51 k and decouple to GNDA with C = 100 nF. Output amplifier stage.
Connect to VDDA with R = 51 k and decouple to GNDA with C = 100 nF. Columns amplifiers stage.
Connect to VDDA with R = 22 k and decouple to GNDA with C = 100 nF. Pre-charge of column
Connect to VDDA with R = 51 k and decouple to GNDA with C = 100 nF. Analog stage of ADC.
Connect to VDDA with R = 230 and decouple to GNDA with C = 100 nF. High level of ADC.
Connect to GNDA with R = 410 and decouple to GNDA with C = 100 nF. Low level of ADC.
Description
Table
Rev. 9 | www.onsemi.com | Page 10 of 34
+4.5
+4.5
+3.3
+3.3
+3.3
8, you can see
Typ
Comment
0
0
0
Table 8
Unit
V
V
V
V
V
V
V
V
are
supply settings listed in
image quality.
Table 9. Dual Shutter Recommended Supply Settings
Image Core Biasing Signals
Table 10
IBIS5-1300. For optimization on speed and power dissipation of
all internal blocks, several biasing resistors are needed.
Each biasing signal determines the operation of a corresponding
module in the sense that it controls the speed and power dissi-
pation. The tolerance on the DC-level of the bias levels can vary
±150 mV due to process variations.
VDDH
VDDR_LEFT
VDDC
VDDA
VDDD
GNDA
GNDD
GND_AB
Parameter
summarizes the biasing signals required to drive the
Voltage on HOLD switches.
Highest reset voltage.
Pixel core voltage.
Analog supply voltage of the
image core.
Digital supply voltage of the
image core.
Analog ground.
Digital ground.
Anti-blooming ground.
High level of DAC.
Low level of DAC.
busses.
Table 9
Description
Related module
to achieve the best possible
NOII5SM1300A
+4.5
+4.5
+3.0
+3.3
+3.3
Typ
DC-Level
0
0
0
1.17 V
1.0 V
3.3 V
0.0 V
1.2 V
1.0 V
1.0 V
2.7 V
1.2 V
Unit
V
V
V
V
V
V
V
V