AT32UC3C2512C-Z2ZT Atmel, AT32UC3C2512C-Z2ZT Datasheet - Page 101

• Manufacturer Part Number: AT32UC3C2512C-Z2ZT
• Description: Microcontrollers (MCU) 512KB FL,-40/125oC AUTO
• Manufacturer: Atmel

Specifications of AT32UC3C2512C-Z2ZT

• Lead Free Status / Rohs Status: Details

10.2.7
10.2.8
10.2.9
10.2.10
9166BS–AVR-02/11
TWIM
TWIS
USBC
WDT
1
2
1
2
3
1
1
SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI
transfer.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low
for the same duration if it is to be receiving data. When TWIS releases TWCK, it releases
TWD at the same time. This can cause a TWI timing violation.
Fix/Workaround
None.
TWALM forced to GND
The TWALM pin is forced to GND when the alternate function is selected and the TWIS
module is enabled.
Fix/Workaround
None.
UPINRQx.INRQ field is limited to 8-bits
In Host mode, when using the UPINRQx.INRQ feature together with the multi-packet mode
to launch a finite number of packet among multi-packet, the multi-packet size (located in the
descriptor table) is limited to the UPINRQx.INRQ value multiply by the pipe size.
Fix/Workaround
UPINRQx.INRQ value shall be less than the number of configured multi-packet.
Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
AT32UC3C
101