EA-XPR-006 Embedded Artists, EA-XPR-006 Datasheet
EA-XPR-006
Specifications of EA-XPR-006
Related parts for EA-XPR-006
EA-XPR-006 Summary of contents
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... The peripheral complement of the LPC11Cx2/Cx4 includes 16/ flash memory data memory, one C_CAN controller, one Fast-mode Plus I RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and general purpose I/O pins. On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included. ...
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... Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities. I data rate of 1 Mbit/s with multiple address recognition and monitor mode. ...
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... LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1 Total UART I ...
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NXP Semiconductors 5. Block diagram LPC11Cx2/Cx4 HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD DTR, DSR, CTS, DCD, RI, RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 (1) CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 2. Pin configuration (LPC11C12/C14) LPC11CX2_CX4 Product data sheet LPC11C12FBD48/301 LPC11C14FBD48/301 ...
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NXP Semiconductors PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 3. Pin configuration (LPC11C22/C24) LPC11CX2_CX4 Product data sheet LPC11C22FBD48/301 LPC11C24FBD48/301 All ...
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... Reset Description state [1] Port 0 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block RESET — External reset input with 20 ns glitch filter. A LOW-going ...
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... O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. Port 1 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block — Reserved. Configure for an alternate function in the IOCONFIG block ...
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... PIO1_11 — General purpose digital input/output pin AD7 — A/D converter, input 7. Port 2 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I PIO2_0 — General purpose digital input/output pin. ...
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... Reset Description state [1] Port 0 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block RESET — External reset input with 20 ns glitch filter. A LOW-going ...
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... CT32B0_MAT3 — Match output 3 for 32-bit timer 0. Port 1 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. All information provided in this document is subject to legal disclaimers. ...
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NXP Semiconductors Table 4. LPC11C22/C24 pin description table Symbol Pin Start logic inputs [5] R/PIO1_0/AD1/ 33 yes CT32B1_CAP0 [5] R/PIO1_1/AD2 CT32B1_MAT0 [5] R/PIO1_2/AD3 CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/ CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP ...
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... SCK0 — Serial clock for SPI0. Port 3 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_4 to PIO3_11 are not available. I/O I ...
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NXP Semiconductors Table 4. LPC11C22/C24 pin description table Symbol Pin Start logic inputs GND [7] XTALIN 6 - [7] XTALOUT [1] Pin state at reset for ...
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... The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral ...
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... Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. • ...
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... Additionally, any GPIO pin (total of 40 pins (LPC11C12/C14 pins (LPC11C22/C24)) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. • ...
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... The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features • ...
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... The I C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... Silent mode A HIGH level on pin STB selects Silent mode. In Silent mode the transmitter is disabled, releasing the bus pins to recessive state. All other functions, including the receiver, continue to operate as in Normal mode. Silent mode can be used to prevent a faulty C_CAN controller from disrupting all network communications. ...
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... It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.13.1 Features • ...
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... Crystal oscillators The LPC11Cx2/Cx4 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11Cx2/Cx4 will operate from the Internal RC oscillator until switched by software ...
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NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) Fig 5. LPC11Cx2/Cx4 clock generation block diagram 7.16.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as ...
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... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. ...
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... Deep power-down mode. 7.17 System control 7.17.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down ...
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... NXP Semiconductors NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip. 7.17.4 Code security (Code Read Protection - CRP) This feature of the LPC11Cx2/Cx4 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted ...
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... All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC11CX2_CX4 Product data sheet Section 7 ...
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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
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NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, ...
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NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level ...
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... Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [ C. [2] T amb [3] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] Pin CAN_RXD pulled LOW externally. [6] BOD disabled. ...
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... R i LPC11CX2_CX4 Product data sheet Conditions ) is the difference between the actual step width and the ideal step width. See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 6. Figure Figure 6. ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 6. ADC characteristics LPC11CX2_CX4 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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NXP Semiconductors 9.2 C_CAN on-chip, high-speed transceiver characteristics Table 8. Static characteristics = 40 C to +85 amb CC ground; positive currents flow into the IC. Also see Symbol Parameter ...
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... Table 8. Static characteristics = 40 C to +85 amb CC ground; positive currents flow into the IC. Also see Symbol Parameter I recessive output current O(rec) I leakage current L R input resistance i R input resistance deviation i R differential input resistance i(dif) C common-mode input i(cm) capacitance ...
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... Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11Cx user manual. 9.4 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11Cx user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. ...
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NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 7. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; ...
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NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. (μA) Fig 10. Deep-sleep mode: Typical supply current I LPC11CX2_CX4 Product data sheet ...
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NXP Semiconductors (μA) Fig 11. Deep power-down mode: Typical supply current I LPC11CX2_CX4 Product data sheet 0 0.6 0.4 0.2 0 −40 −15 different supply voltages V DD All information provided in this document is subject to legal ...
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... NXP Semiconductors 9.5 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements ...
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NXP Semiconductors 9.6 Electrical pin characteristics V Fig 12. High-drive output: Typical HIGH-level output voltage V (mA) Fig 13. I LPC11CX2_CX4 Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 ...
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NXP Semiconductors (mA) Fig 14. Typical LOW-level output current I V Fig 15. Typical HIGH-level output voltage V LPC11CX2_CX4 Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. ...
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NXP Semiconductors (μA) Fig 16. Typical pull-up current I (μA) Fig 17. Typical pull-down current I LPC11CX2_CX4 Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions ...
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... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 18. External clock timing (with an amplitude of at least V LPC11CX2_CX4 Product data sheet Flash characteristics ...
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... Symbol Parameter f osc(int) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. [2] The typical frequency spread over processing and temperature (T [3] See the LPC11Cx user manual. LPC11CX2_CX4 Product data sheet Dynamic characteristic: internal oscillators ...
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... SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. ...
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... LOW period (t data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal ...
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NXP Semiconductors Table 18. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data output hold time in SPI ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SPI slave timing in SPI mode LPC11CX2_CX4 Product data sheet T cy(clk) MOSI DATA VALID t MISO DATA VALID MOSI DATA VALID t v(Q) MISO DATA VALID Pin ...
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... C mode, a minimum of 200 mv (RMS) is needed. Fig 23. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...
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NXP Semiconductors Fig 24. Oscillator modes and models: oscillation mode of operation and external crystal Table 19. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 ...
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... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 25 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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NXP Semiconductors 11.5 Reset pad configuration Fig 26. Reset pad configuration 11.6 C_CAN with external transceiver (LPC11C12/C14 only) Fig 27. Connecting the C_CAN to an external transceiver (LPC11C12/C14) LPC11CX2_CX4 Product data sheet reset GLITCH FILTER BAT 3 ...
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NXP Semiconductors 11.7 C_CAN with on-chip, high-speed transceiver (LPC11C22/C24 only) Fig 28. Connecting the CAN high-speed transceiver to the CAN bus (LPC11C22/C24) LPC11CX2_CX4 Product data sheet CANH CANH CAN HIGH-SPEED TRANSCEIVER CANL ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 13. Soldering Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 30. Reflow soldering of the LQFP48 package LPC11CX2_CX4 Product data sheet (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
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... Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus Application Programming Interface BrownOut Detection Controller Area Network General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Service Data Object Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Universal Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 3 — ...
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... NXP Semiconductors 15. Revision history Table 22. Revision history Document ID Release date LPC11CX2_CX4 v.3 20110627 Modifications: LPC11CX2_CX4 v.2 20101203 Modifications: LPC11C12_C14 v.1 20100921 LPC11CX2_CX4 Product data sheet Data sheet status Product data sheet • C-bus pins configured as standard mode pins, parameter I (minimum) for 2.0 V V ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 17. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC11CX2_CX4 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 7.10 I C-bus serial I/O controller . . . . . . . . . . . . . . 18 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 C_CAN controller . . . . . . . . . . . . . . . . . . . . . . 19 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11.2 On-chip, high-speed CAN transceiver . . . . . . 20 7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.3 Silent mode 7.11.2.4 Undervoltage protection . . . . . . . . . . . . . . . . . 20 7.11.2.5 Thermal protection . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.6 Time-out function . . . . . . . . . . . . . . . . . . . . . . 21 7.12 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LPC11Cx2/Cx4 32-bit ARM Cortex-M0 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved ...