AN983BLX-BG-T-V1 Infineon Technologies, AN983BLX-BG-T-V1 Datasheet - Page 85

• Manufacturer Part Number: AN983BLX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-FQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BLX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BLXBGTV1; SP000076446

9.3
Table 15
Module
PHY
Table 16
Register Short Name
R0
R1
R2
R3
R4
R5
R6
The register is addressed wordwise.
Standard abbreviations:
Table 17
Mode
read/write
read
write
read/write
hardware
affected
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Data Sheet
PHY Registers(Accessed by CSR9 MDI/MMC/MDO/MDC)
Registers Address Space
Registers Overview
Registers Access Types
Symbol Description Hardware (HW)
rw
r
w
rwh
rwv
ro
rv
lhsc
llsc
lhmk
Base Address
0000 0000
Register Long Name
Register 0(MII Control)
Register 1(Status)
Register 2
Register 3
Register 4
Register 5
Register 6
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register can be modified by HW
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Registers and Descriptors DescriptionPHY Registers(Accessed by CSR9
H
End Address
0000 0006
85
H
Description Software (SW)
Register is readable and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
Register is writable by SW
Register can be modified by HW, but the
priority SW versus HW has to be specified
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
Note
Offset Address
0
1
2
3
4
5
6
H
H
H
H
H
H
H
Rev. 1.81, 2005-12-15
Page Number
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AN983B/BX