AN983BL ETC-unknow, AN983BL Datasheet
AN983BL
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... AN983B/AN983BL PCI/miniPCI-to-Ethernet LAN Controller DATASHEET Rev. 1.8 MAY. 2003 ADMtek .com.tw Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." ADMtek reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them ...
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AN983B Datasheet Revision History Revision Date Revision 0.1 Oct, 2000 1.0 Feb, 2001 1.1 Mar, 2001 1.2 Sep, 2001 1.3 Sep, 2001 1.4 Sep, 2001 1.5 JULY, 2002 1.6 JULY, 2002 1.7 JULY, 2002 1.8 MAY, 2003 Rev. 1.8 PCI/miPCI ...
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AN983B CONTENTS Datasheet Revision History................................................................................. 2 1. GENERAL DESCRIPTIONS...................................................................................... 9 2. SYSTEM BLOCK DIAGRAM.................................................................................. 10 3. FEATURES ................................................................................................................. 11 I ............................................................................................ 11 NDUSTRY STANDARD FIFO...................................................................................................................... 11 PCI I/F................................................................................................................... 11 EEPROM/B ROM I/F .................................................................................... 11 OOT MAC/P .................................................................................................... 12 HYSICAL LED ...
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AN983B CR13 (offset = 34h Capabilities Pointer. ............................................... 25 CR15 (offset = 3ch Configuration Interrupt............................................ 25 CR16 (offset = 40h Driver Space for special purpose. .......................... 25 CR32 (offset = 80h), SIG - Signature ...
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AN983B CSR26 (offset = a8h) - PAR1, physical address register 1............................... 44 CSR27 (offset = ach) - MAR0, multicast address register 0 ............................ 45 CSR28 (offset = b0h) - MAR1, multicast address register 1............................ 45 Operation Mode Register (Memory base ...
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... Timing Specifications........................................................................................ 79 PCI Clock Specifications .................................................................................. 79 PCI Timings ...................................................................................................... 80 Flash Interface Timings .................................................................................... 81 EEPROM Interface Timings (AC/AD)............................................................. 83 11. PACKAGE................................................................................................................. 87 Dimensions for 128 –pin PQFP Package(AN983B)......................................... 87 Dimensions for 128 –pin LQFP Package(AN983BL) ...................................... 88 12. LAYOUT GUIDE (REV.1.0B) Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY .................................................................................. 89 ADMtek Inc. ...
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AN983B Layout Guide Revision History: ....................................................................... 89 12.1 placement .......................................................................................................... 89 12.2 trace routing...................................................................................................... 89 12.3 Vcc and GND .................................................................................................... 90 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc. www.admtek.com.tw 7 ...
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... Fig - 23 MDIO sourced by MAC……………………………………………………………..87 MDIO sourced by PHY …...… Fig - 24 Package outline for the AN983B/AN983BL …... Fig - 25 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY … ...
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AN983B 1. GENERAL DESCRIPTIONS The AN983B is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. The AN983B was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for ...
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AN983B 2. SYSTEM BLOCK DIAGRAM EEPROM AN983B 25MHz Crystal Fig - 1 System diagram of the AN983B Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Boot ROM LEDs ADMtek Inc. www.admtek.com.tw RJ-45 10 ...
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AN983B 3. FEATURES INDUSTRY STANDARD IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX PCI Specification 2.2 compliant ACPI and PCI power management Ver.1.1 compliant Support PC99 wake on LAN FIFO ...
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AN983B Provides serial interface for read/write 93C46/66 EEPROM Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment. MAC/PHYSICAL Integrates the whole ...
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AN983B 4. BLOCK DIAGRAM egiste rs C ontrol I/F T ran sit C on trol B oot ontrol I ...
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... PIN ASSIGNMENT DIAGRAM 1 bra 13 2 bra 14 3 bra 15 4 VAAR 5 TST3 6 RXIN 7 RXIP 8 GNDR 9 TST0 10 TST1 11 TST2 GNDREEF 15 RIBB 16 VAAREF 17 XTLN 18 XTLP AN983B/AN983BL 19 GNDT 20 TXOP 21 TXON 22 VAAT 23 Vdd-IR 24 INTA# 25 RST# 26 Vss-IR 27 pci_clk 28 Vdd-pci 29 gnt# 30 req# 31 pme# 32 Vss-pci 33 AD31 34 AD30 35 AD29 36 AD28 ...
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AN983B 6. PIN DESCRIPTION Pin # Name Type Description PCI INTERFACE 24 INTA# O/D PCI interrupt request. AN983B asserts this signal when one of the interrupt events occurs. PCI signal to initialize the AN983B. The active reset signal should be ...
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AN983B 43 C-BEB3 I/O Bus command and byte enable 57 C-BEB2 69 C-BEB1 83 C-BEB0 44 IDSEL I Initialization Device Select. This signal is asserted when host issues the configuration cycles to the AN983B. 59 FRAME# I/O Begin and duration ...
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AN983B 115 BrWE# O BootROM Write Enable for flash ROM application. MII INTERFACE (PROGRAM AN983B AS MAC-ONLY MODE, SET FCH [2:0] = 100B) 127 Mdc O MII Management Data Clock 126 Mtxen O MII Transmit Enable 109,110 MtxD0~3 O MII ...
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AN983B will be driven on with 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. 104 Led-100Lnk O 4Leds mode: LED display for 100Mb/s speed. This pin will be driven on (Led-speed) continually when ...
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AN983B 7. REGISTERS AND DESCRIPTORS DESCRIPTION There are three kinds of registers designed for AN983B. They are AN983B configuration registers, PCI control/status registers, and Transceiver control/status registers. The AN983B configuration registers are used to initialize and configure the AN983B for ...
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AN983B 7.1 AN983B CONFIGURATION REGISTERS With the configuration registers software driver can initialize and configure AN983B. All of the contents of configuration registers are set to default value when there is any hardware reset occurs. On the other hand, there ...
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AN983B 7.1.2. AN983B CONFIGURATION REGISTERS TABLE Offset b31 ----------- 00h Device ID* 04h Status 08h Base Class Subclass Code 0ch ------ ------ 10h Base I/O address 14h Base memory address 18h~ Reserved 24h 28h ROM-im* Address space offset* 2ch Subsystem ...
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AN983B 7.1.3 AN983B CONFIGURATION REGISTERS DESCRIPTIONS CR0 (offset = 00h), LID - Loaded Identification number of Device and Vendor Bit # Name Descriptions LDID Loaded Device ID, the device ID number loaded from serial 31~16 EEPROM. LVID Loaded Vendor ID, ...
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AN983B 1: the AN983B provides the PCI management function 0: the AN983B doesn’t provide New Capabilities. --- Reserved. 19~ 9 CSE Command of System Error Response 8 1: enable system error response. AN983B will assert SERR# When it find a ...
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AN983B timer expires and the AN983B still asserted FRAME#, then the AN983B will terminate the data transaction as soon as its GNT# is removed. CLS Cache Line Size. This value specifies the system cache line size in ...
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AN983B BRE Boot ROM Enable. The AN983B really enables its boot ROM 0 access only if both the memory space access bit (bit 1 of CR1) and this bit are set enable Boot ROM. (Combines with bit ...
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AN983B CR48 (offset = c0h), PMR0, Power Management Register0. Bit # Name Descriptions PMES PME_Support. 31~27 The AN983B will assert PME# signal while in the D0, D1, D2, D3 power state. The AN983B supports Wake-up from the above states. D2S ...
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AN983B interpreting the value of the Data register. This field is required for any function that implements the Data register. Otherwise, it’s optional. The AN983B doesn’t support Data register and Data_Scale. DSEL Data_Select, This four-bit field is used to select ...
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AN983B 7.2. PCI CONTROL/STATUS REGISTERS 7.2.1. PCI CONTROL/STATUS REGISTERS LIST Offset from Index Name base address of CSR CSR0 PAR 00h CSR1 TDR 08h CSR2 RDR 10h CSR3 RDB 18h CSR4 TDB 20h CSR5 SR 28h CSR6 NAR 30h CSR7 ...
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AN983B 7.2.2. CONTROL/STATUS REGISTER DESCRIPTION CSR0 (offset = 00h), PAR - PCI Access Register Bit # Name Descriptions --- Reserved 31~25 MWIE Memory Write and Invalidate Enable enable AN983B to generate memory write invalidate command. AN983B will generate ...
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AN983B DSL Descriptor Skip Length. Defines the gap between two descriptions in the units of DW. BAR Bus arbitration 1 0: receive higher priority 1: transmit higher priority SWR Software reset 0 1: reset all internal hardware, ...
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AN983B 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved TS Transmit State. Report the current transmission state only, 22 interrupt will be generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill, read ...
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AN983B --- Reserved 12 GPTT General Purpose Timer Time-out, base on CSR11 timer 11 register --- Reserved 10 RWT Receive Watchdog Time-out, based on CSR15 watchdog timer 9 register RPS Receive Process Stopped, receive state = stop 8 RDU Receive ...
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AN983B --- Reserved 31~22 SF Stor e and forward for transmit 21 0: disable 1: enable, ignore the transmit threshold setting --- Reserved 20 SQE SQE Disable 19 0: enable SQE function for 10BASE-T operation. The AN983B provides SQE test ...
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AN983B 0: filters all bad packets --- Reserved 2 SR Start/Stop Receive 1 0: receive processor will enter stop state after the current reception frame completed. This value is effective only when the receive processor is in the running or ...
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AN983B 1: combine this bit and bit 16 of CSR7 to enable receive completed interrupt. TUIE Transmit Under-flow Interrupt Enable 5 1: combine this bit and bit 15 of CSR7 to enable transmit under-flow interrupt. --- Reserved 4 TJTTIE Transmit ...
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AN983B --- Reserved 15 SRC Serial EEPROM Read Control 14 Set together with CSR9 bit11 to enable read operation from EEPROM SWC Serial EEPROM Write Control 13 Set together with CSR9 bit11 to enable write operation to EEPROM --- Reserved ...
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AN983B WP4E Wake-up Pattern Four Matched Enable. 26 WP5E Wake-up Pattern Five Matched Enable. 25 --- Reserved 24-18 LinkOFF Link Off Detect Enable. The AN983B will set the LSC bit of 17 CSR13 after it has detected that link status ...
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AN983B 0008h 000ch 0010h CRC16 of pattern 1 0014h 0018h 001ch 0020h 0024h CRC16 of pattern 2 0028h 002ch 0030h 0034h 0038h CRC16 of pattern 3 003ch 0040h 0044h 0048h 004ch CRC16 of pattern 4 0050h 0054h 0058h 005ch 0060h ...
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AN983B watchdog timer from last carrier deserted bit-time 1: 48 bit-time RWD Receive Watchdog Disable the receiving packet bytes, the watchdog timer will be expired. 1: disable the receive watchdog. --- Reserved 3 JCLK Jabber ...
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AN983B AAISS Added Abnormal Interrupt Status Summary any of added abnormal interrupt happened. These bits are the same as the status register of CSR5. You 14~0 can access those status bits through either CSR5 or CSR16. LH* = ...
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AN983B PWRS_clr 1: PCI_reset rising will automatically reset CR49/ PWRS[1: 00h. Pmes_stic 1: pmez sticky: While pmez signal is asserted by wake event, it cannot be auto de-asserted. The software should clear CR49<15> PMES bit ...
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AN983B 0: de-assert pmez signal RWP Reset Wake-up Pattern Data Register Pointer 6 0: Normal 1: Reset PAUSE PAUSE function control to disable or enable the PAUSE 5 function for flow control. The default value of PAUSE is decided by ...
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AN983B effect. Since the AN983B doesn’t supports PME# from D3cold, this bit is defaulted to “0”. DSCAL Data_Scale, indicates the scaling factor to be used when 14,13 interpreting the value of the Data register. This field is required for any ...
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AN983B TBCNT Transmit Burst Count 20~16 After this number of consecutive successful transmit, transmit completed interrupt will be generated. Continuously do this function if no reset. TTO Transmit Time-Out = (deferred time + back-off time). 11~0 When the TDIE (bit28 ...
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AN983B For example, physical address = 00-00-e8-11-22-33 PAR0 PAR1 PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17=000). CSR27 (offset = ach) ...
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AN983B CSR_30(offset = b8h) - UAR1, unicast address register 1 Bit # Name Descriptions UAB7 Unicast address byte 7 (hash table 63:56) 31~24 23~16 UAB6 Unicast address byte 6 (hash table 55:48) 15~8 UAB5 Unicast address byte 5 (hash table ...
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AN983B 7.3. PHY REGISTERS (ACCESSED BY CSR9 MDI/MMC/MDO/MDC) 7.3.1. TRANSCEIVER REGISTERS DESCRIPTIONS Register 0 (MII Control) BIT NAME 15 Reset 14 Loopback 13 Speed selection 12 Autonegotiation enable 11 Power down 10 Isolate 9 Restart autonegotiation 8 Duplex mode 7 ...
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AN983B When set inhibits actual transmission on the wire. Speed selection Forces speed of Phy only when autonegotiation is disabled. The default state of this bit will be determined by a power-up configuration pin in this case. Otherwise it defaults ...
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AN983B duplex 8-7 Reserved 6 MF Preamble 1 = PHY can accept management frames Suppression with preamble suppression 0 = PHY cannot accept management frames with preamble suppression 5 Autoneg Complete 1 = autoneg completed autoneg incomplete 4 ...
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AN983B (bits 5-0) 3:0 PHY_ID[3-0] Revision Number (bits 3-0); Register 3, bit bit of PHY Identifier This uses the OUI of ADMtek, device type of 1 and rev 0. Register 4 BIT NAME DESCRIPTION 15 Next Page ...
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AN983B The contents of this register should not be relied upon unless register 1 bit 5 is set (autoneg complete). After negotiation this register should contain a copy of the link partner’s register 4. All bits are therefore defined in ...
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AN983B The AN983B provides receive and transmit descriptors for packet buffering and management. 7.4.1 RECEIVE DESCRIPTOR ...
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AN983B FS First descriptor Last descriptor Too long packet (packet length > 1518 bytes). This bit is valid only in last descriptor 7 CS Late collision. Set when collision is active after 64 bytes. This bit ...
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AN983B Own Status TDES0 Control TDES1 Buffer1 address TDES2 Buffer2 address TDES3 Descriptor addresses must be longword alignment ...
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AN983B TER End of Ring 25 TCH 2nd address chain 24 Indicate the buffer2 address is the next descriptor address DPD Disable padding function 23 --- Reserved 22 TBS2 Buffer 2 size 21-11 TBS1 Buffer 1 size 10-0 TDES2 Bit ...
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AN983B 8. FUNCTIONAL DESCRIPTIONS 8.1 INITIALIZATION FLOW The flow of initialize AN983B is shown as below. Need setting media type? Read EEPROM from CSR9 Set Physical address (CSR25, 26) Need setting Multicast? Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated ...
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AN983B 8.2 NETWORK PACKET BUFFER MANAGEMENT 8.2.1 DESCRIPTOR STRUCTURE TYPES For networking operation, the AN983B transmits the data packet from transmit buffers in host memory to AN983B’s transmit FIFO and receives the data packet from AN983B’s receive FIFO to receive ...
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AN983B Chain structure There is only one buffer per descriptor in chain structure. CSR3 or CSR4 Descriptor Pointer Fig - 6 Chain structure of frame buffer Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Descriptor own Data Buffer --- ...
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AN983B 8.2.2 THE POINT OF DESCRIPTOR MANAGEMENT OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access Transmit Descriptor Pointers next packet to be transmitted own bit=2, packet1 and packet 2 are ...
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AN983B Receive Descriptor Pointers own bit=1, next descriptor ready for incoming packet filled descriptor pointer end of ring Fig - 8 Receive pointers for descriptor management Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Descriptor 0 Data Buffer Packet ...
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AN983B 8.3 TRANSMIT SCHEME AND TRANSMIT EARLY INTERRUPT 8.3.1 TRANSMIT FLOW The flow of packet transmit is shown as below. AN983B read descriptor available descriptor(own=1) read data and put into tx fifo no deferring and greater than tx threshold DO ...
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AN983B place the 1st packet data into host memory issue transmit demand FIFO-to-host memory operation (1st packet) Transmit enable place the 2nd packet data into host memory check point FIFO-to-host memory operation (2nd packet) place the 3rd packet data into ...
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AN983B 8.4 RECEIVE SCHEME AND RECEIVE EARLY INTERRUPT SCHEME The following figure shows the difference of timing without early interrupt and with early interrupt. incoming packet receive FIFO operation FIFO-to-host memory operation interrupt driver read header higher layer process driver ...
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AN983B FIFO-to-host memory operation receive early interrupt driver read header(early) higher layer process(early) driver read the rest data tim e Fig - 13 Detailed receive early interrupt flow Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY The size of ...
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AN983B 8.5 NETWORK OPERATION 8.5.1 MAC OPERATION In the MAC (Media Access Control) portion of AN983B, it incorporates the essential protocol requirements for operating as an IEEE802.3 and Ethernet compliant node. Format Field Description A 7-byte field of (10101010b) Preamble ...
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AN983B 1. IFG1 time (64-bit time carrier is detected on the medium during this time, the AN983B will reset the IFG1 time counter and restart to monitor the channel for an idle again. 2. IFG2 time (32-bit time): ...
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AN983B Start-of-Stream Delimiter-SSD (/J/K transmission stream, the first 16 nibbles are MAC preamble. In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the transceiver will replace the first 2 ...
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AN983B cabling reliable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to perform these functions. MLT3 to NRZI Decoder and PLL for ...
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AN983B NRZ to NRZI converter then loop-back to the receive path into the input of NRZI to NRZ converter. In the 10BASE-T loop-back operation, the data is through transmitting path and loop-back from the output of the Manchester encoder into ...
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AN983B The PAUSE function operation is used to inhibit transmission of data frames for a specified period of time. The AN983B supports full duplex protocol of IEEE802.3x. To support PAUSE function, the AN983B implements the MAC Control Sub-layer functions to ...
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AN983B the AN983B ends the PAUSE state immediately. Wait for Transmission Completed transmission_in_progress = false* DA=(01-80-C2-00-00-01 + Phys-address) PAUSE FUNCTION n_slots_rx=data[17:32] Start pause_timer(n_slots_rx*slot_time) UCT Fig - 15 PAUSE operation receive state diagram Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated ...
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AN983B 8.6 LED DISPLAY OPERATION The AN983B provides 2 kinds of LED display mode; the detail descriptions about the operation are described in the PIN Description section. 8.6.1 FIRST MODE - 3 LED DISPLAYS FOR 100Mbps(on) or 10Mbps(off) Link (Keeps ...
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AN983B contains to default value then clear the bit 15 of PHY register 8.8 WAKE ON LAN FUNCTION The AN983B can assert a signal to wake up the system when it received a Magic Packet from the ...
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AN983B Compatibility with PCI CLKRUN scheme. 8.9.1 POWER STATES DO (Fully On) In this state the AN983B operates as full functionality and consumes its normal power. While in the D0 state, if the PCI clock is lower than 16MHz, the ...
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AN983B B2 maintained and Rx B0, B1, Configuration lost, full D3hot B2 initialization required upon return All configurations lost. D3cold Power-on defaults in place on return to D0 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with ...
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AN983B 9. GENERAL EEPROM FORMAT DESCRIPTION Connection Type Definition Offset Length Description 2 AN983B Signature: 0x85, 0x09, AN985 Signature: 0x85, 0x19 0 1 Format major version: 0x02 Format minor version: 0x00 3 4 Reserved 4 6 IEEE network ...
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AN983B 0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Software Driver Default Auto-Negotiation Power-on Auto-detection Auto Sense 10BaseT BNC AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT Full Duplex ...
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AN983B 10. ELECTRICAL SPECIFICATIONS AND TIMINGS 10.1 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection 10.2 DC SPECIFICATIONS General DC Specifications Parameter Description Supply Voltage Vcc Power Supply Icc PCI Interface DC ...
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AN983B Input Pin Capacitance Cinf 10.3 AC SPECIFICATIONS PCI Signaling AC Specifications for 3.3V Parameter Description Switching Current High Ioh (AC) Switching Current Low Iol (AC) Slew Rate Unloaded Output Rise Time Tr Unloaded Output Fall Time Tf 10.4 TIMING ...
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AN983B PCI Timings Parameter Description Access time – bused signals Tval Access time –point to point Tval (ptp) Float to Active Delay Ton Active to Float Delay Toff Input Set up Time to Clock – Tsu bused signals Input Set ...
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AN983B CLK OUTPUT Delay Tri-state OUTPUT INPUT 1.5V Flash Interface Timings Parameter Description Read cycle time Trc Chip enable access time Tce Address access time Taa Output enable access time Toe #CE low to active output Tclz #OE low to ...
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AN983B #WE and #CE hold time Tch #OE high setup time Toes #OE high hold time Toeh #CE pulse width Tcp #WE pulse width Twp #WE high width Twph Data setup time Tds Data hold time Tdh Byte load cycle ...
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AN983B ADDRESS Trc CS# OE# DATA EEPROM Interface Timings (AC/AD) Parameter Description Serial Clock Frequency Tscf Delay from CS High to SK High 2.7V<Vcc<5.5V Tecss Delay from SK Low to CS Low 2.7V<Vcc<5.5V Tecsh Setup Time ...
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AN983B CS Tecss CLK Tedts DI Fig - 20 Serial EEPROM timing MII Interface Timing TX_CLK TXD<3:0>,TX_EN, TX_ER 0 ns Min 25 ns MAX Fig- 21 Transmit signal timing relationships at the MII Rev. 1.8 PCI/miPCI Fast Ethernet Controller with ...
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AN983B RX_CLK RXD<3:0>,RX_DV, RX_ER Fig- 22 Receive signal timing relations at the MII MDC MDIO 10 ns MIN Fig- Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY 10 ns MIN 23 MDIO sourced by STA ADMtek Inc. www.admtek.com.tw V ...
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AN983B MDC MDIO 0 ns Min 300 ns MAX FIG- 24 MDIO SOURCED BY PHY Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc. www.admtek.com.tw V ih(min) V il(max) V ih(min) V il(max) 86 ...
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... AN983B 11. PACKAGE Fig - 25 Package outline for the AN983B / AN983BL Dimensions for 128 –pin PQFP Package (AN983B) Symbol Description Overall Height A Stand Off A1 Lead Width b Lead Thickness c Terminal Dimension 1 D Package Body 1 D1 Terminal Dimension 2 E Package Body 2 E1 Lead Pitch ...
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... AN983B Dimensions for 128 –pin LQFP Package (AN983BL) Symbol Description Overall Height A Stand Off A1 Lead Width b Lead Thickness c Terminal Dimension 1 D Package Body 1 D1 Terminal Dimension 2 E Package Body 2 E1 Lead Pitch e1 Foot Length L1 Lead Angle T Coplanarity Y Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ...
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AN983B 12. LAYOUT GUIDE (REV.1.0B) Layout Guide Revision History: Revision Date Revision 1.0b October, 2000 12.1 PLACEMENT Keep the distance as short as possible between Centaur-P and transformer, as well as transformer and RJ45. Make crystal device cross to Centaur-P ...
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AN983B 6). Keep the distance between the Tx and Rx differential pairs large, even separate ground planes underneath Tx and Rx signal pairs. 7). Away from clock and power trace. 8). If possible, with GND plane around. 9 ...
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AN983B 4). Provide sample power and ground planes Power Trace AN983B VCC FROM PCI Not Suggestted GND plane 1 good idea to fill in unused areas of the signal planes with solid copper 2). The signal ground ...