PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 83
PEB22504HT-V11
Manufacturer Part Number
PEB22504HT-V11
Description
IC INTERFACE QUAD 100-TQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB22504HT-V11.pdf
(128 pages)
Specifications of PEB22504HT-V11
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB22504HT-V11
PEB22504HT-V11IN
PEB22504HT-V11IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB22504HT-V11
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Command Register (Read/Write)
Addresses: 13
Value after reset: 00
CMDR
RES
IBV
IPE
CEB
DBEC
DCVC
Data Sheet
RES
7
H
, 33
Note: The maximum time between writing to the CMDR register and
Reset Receiver and Transmitter
The receive and the transmit line interface (except the clock and data
recovery unit DPLL) are reset. The contents of the control registers is
not deleted.
Insert Bipolar Violations
Setting this bit forces a bipolar violation in the transmit data stream.
Violations are inserted at the next possible position. Ones preceded
by two or more zeros are not converted into violations.
Example (V = inserted violation):
001000010100 is converted to 001000010V00
Insert PRBS Error
Setting this bit forces a PRBS error in the outgoing data stream (if
PRBS transmission is enabled).
Center Elastic Buffer
Setting this bit forces the delay through the elastic buffer to half of the
current buffer size (LOOP.BS1/0).
Disable Pseudo-Random Binary Sequence Error Counter
This bit is only valid if LIM1.ECM is cleared. It must be set before
reading the error counter. This bit is reset automatically if the
corresponding error counter high byte has been read. With the rising
edge of this bit the error counter is latched and then cleared.
Disable Code Violation Counter
See bit DBEC.
H
H
, 53
H
the execution of the command takes 2.5 periods of the current
line data rate. Register bits are set by software and reset by
hardware automatically after the required operation has been
completed. Register bits in CMDR cannot be reset by software.
, 73
H
IBV
83
IPE
CEB
DBEC
Register Description
QuadLIU V1.1
DCVC
0
PEB 22504
2001-02
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