CLC012AJE-TR13/NOPB National Semiconductor, CLC012AJE-TR13/NOPB Datasheet - Page 11

• Manufacturer Part Number: CLC012AJE-TR13/NOPB
• Description: IC CABLE EQUALIZER ADAPT 14-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC012AJE-TR13/NOPB

• Applications: Medical
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Mounting Type: Surface Mount
• For Use With: SD012EVK - BOARD EVALUATION CLC012DRIVECABLE02EVK - BOARD EVAL SERDES, CLC001, 012
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Other names: *CLC012AJE-TR13; *CLC012AJE-TR13/NOPB; CLC012AJE-TR13

Design Guidelines
Junction Temperature =
Layout and Measurement
The printed circuit board layout for the CLC012 requires
proper high-speed layout to achieve the performance speci-
fications found in the datasheet. The following list contains a
few rules to follow:
1. Use a ground plane.
2. Decouple power pins with 0.1 µF capacitors placed
3. Design transmission strip lines from the CLC012’s input
Troubleshooting with scope probes can affect the equaliza-
tion. For high data rates, use a low capacitance probe with
less than 2 pF probe capacitance. Evaluation boards and
literature are available for quick prototyping and evaluation
of the CLC012 Adaptive Cable Equalizer. The CLC012 con-
tains CMOS devices and operators should use grounding
straps when handling the parts.
Figure 9 shows the CLC012’s internal power supply routing.
Bypass V
• Monolithic capacitor of about 0.1 µF placed less than 0.1”
• Tantalum capacitor of about 6.8 µF for large current
P
(θ
(3mm) from the pin
signal swings placed as close as convenient to the
CLC012
DMAX
JA
≤ 0.1” (3mm) from the power pins.
and output pins to the board connectors.
)(278 mW) + T
= P
CC
(pin 4) by:
T
–P
L
= 278 mW
A
= T
A
+ 26˚C
(Continued)
FIGURE 8. Typical Measurement Block
10014528
11
4. Route outputs away from inputs.
5. Keep ground plane ≥ 0.025” (0.06mm) away from the
Figure 8 shows a block level measurement diagram, while
Figure 15 on depicts a detailed schematic. A pseudo-random
pattern generator with low output jitter was used to provide a
NRZI pattern to create the eye diagrams shown in the Typi-
cal Performance Characteristics section.
Since most pattern generators have a 50Ω output imped-
ance, a translation can be accomplished using a CLC005
Cable Driver as an impedance transformer. A wide band-
width oscilloscope is needed to observe the high data rate
eye pattern. When monitoring a single output that is termi-
nated at both the equalizer output and the oscilloscope, the
effective output load is 37.4Ω. Consequently, the signal
swing is half that observed for a single-ended 75Ω
termination.
To minimize ringing at the CLC012’s inputs, place a 100Ω
resistor in series with the input. This resistor reduces induc-
tance effects.
input and output pads.
FIGURE 9. Power Package Routing Fixture
www.national.com
10014529