UJA1065TW/5V0,512 NXP Semiconductors, UJA1065TW/5V0,512 Datasheet

Page 1

UJA1065 High-speed CAN/LIN fail-safe system basis chip Rev. 07 — 25 February 2010 1. General description The UJA1065 fail-safe System Basis Chip (SBC) replaces basic discrete components that are common in every Electronic Control Unit (ECU) with a Controller Area ...

Page 2

... NXP Semiconductors 2. Features 2.1 General Contains a full set of CAN and LIN ECU functions: CAN transceiver and LIN transceiver Voltage regulator for the microcontroller (3 5.0 V) Separate voltage regulator for the CAN transceiver (5 V) Enhanced window watchdog with on-chip oscillator Serial Peripheral Interface (SPI) for the microcontroller ...

Page 3

... NXP Semiconductors 2.4 Power management Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep mode Local wake-up input with cyclic supply feature Remote wake-up capability via the CAN-bus and LIN-bus External voltage regulators can easily be incorporated in the power supply system ...

Page 4

... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1065TW HTSSOP32 [1] UJA1065TW/5V0 is for the 5 V version; UJA1065TW/3V3 is for the 3.3 V version. 4. Block diagram 31 SENSE 32 BAT42 27 BAT14 29 SYSINH INH/LIMP 7 INTN 18 WAKE WAKE 16 TEST CHIP TEMPERATURE 11 SCK 9 SDI SPI 10 SDO 12 SCS ...

Page 5

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCS TXDC RXDC n.c. TEST UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip n. TXDL 4 V1 RXDL ...

Page 6

... NXP Semiconductors Table 2. Symbol INH/LIMP WAKE n.c. V2 CANH CANL GND SPLIT LIN RTLIN BAT14 n.c. SYSINH V3 SENSE BAT42 The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND for the best EMC performance ...

Page 7

... NXP Semiconductors 6. Functional description 6.1 Introduction The UJA1065 combines all peripheral functions around a microcontroller within typical automotive networking applications into one dedicated chip. The functions are as follows: • Power supply for the microcontroller • Power supply for the CAN transceiver • ...

Page 8

... NXP Semiconductors mode change via SPI watchdog trigger Normal mode V1: ON SYSINH: HIGH CAN: all modes available flash entry enabled (111/001/111 mode sequence) LIN: all modes available OR mode change to Sleep with pending wake-up watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW init Normal mode ...

Page 9

... NXP Semiconductors 6.2.1 Start-up mode Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support different software initialization cycles that depend on the reset event ...

Page 10

... NXP Semiconductors Entering Normal mode does not activate the CAN or LIN transceiver automatically. The CAN Mode Control (CMC) bit must be used to activate the CAN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus. The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus ...

Page 11

... NXP Semiconductors When an interrupt event occurs the application software has to read the Interrupt register within t RSTN(INT) entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into Normal mode via an SPI access or to stay in Standby mode ...

Page 12

... NXP Semiconductors 6.2.7 Flash mode Flash mode can only be entered from Normal mode by entering a specific Flash mode entry sequence. This fail-safe control sequence comprises three consecutive write accesses to the Mode register, within the legal windows of the watchdog, using the operating mode codes 111, 001 and 111 respectively result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (bits RSS[3:0] = 0110) ...

Page 13

... NXP Semiconductors The following corrupted watchdog accesses result in an immediate system reset: • Illegal watchdog period coding; only ten different codes are valid • Illegal operating mode coding; only six different codes are valid Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register ...

Page 14

... NXP Semiconductors The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period ...

Page 15

... NXP Semiconductors If the microcontroller supply current increases above I the watchdog is restarted with the last used watchdog period time and a watchdog restart interrupt is forced, if enabled. In case of a direct mode change towards Standby mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active ...

Page 16

... NXP Semiconductors The behavior of pin RSTN is illustrated in setting of the RLC bit (defines the reset length). Once an external reset event is detected the system controller enters the Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in mode is entered as shown RSTN Fig 6. Fig 7. ...

Page 17

... NXP Semiconductors Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than t immediately enters Fail-safe mode since this indicates an application failure. The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin ...

Page 18

... NXP Semiconductors A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events lower than V case one of the lower V1 undervoltage reset thresholds is selected. The V1 regulator is overload protected. The maximum output current available from pin V1 depends on the voltage applied to pin BAT14 according to the characteristics section. ...

Page 19

... NXP Semiconductors 6.7 CAN transceiver The integrated high-speed CAN transceiver of the UJA1065 is an advanced ISO 11898-2 and ISO 11898-5 compliant transceiver. In addition to standard high-speed CAN transceivers the UJA1065 transceiver provides the following features: • Enhanced error handling and reporting of bus and RXD/TXD failures; these failures are separately identified in the System Diagnosis register • ...

Page 20

... NXP Semiconductors Normal mode OR Flash mode AND CMC = 1 Normal mode OR Flash mode AND CMC = 0 AND CPNC = 0 On-line mode V2: ON/OFF (V2C/V2D) transmitter: OFF RXDC: wake-up (active LOW) SPLIT: ON/OFF (CSC/V2D) CPNC = 0 no activity for t > t CAN wake-up filter passed AND CPNC = 0 power-on Fig 8 ...

Page 21

... NXP Semiconductors When leaving Active mode the CAN transmitter is disabled and the CAN receiver is monitoring the CAN-bus for a valid wake-up. The CAN termination is then working autonomously. 6.7.1.2 On-line mode In On-line mode the CAN-bus pins and pin SPLIT (if enabled) are biased to the normal levels ...

Page 22

... NXP Semiconductors Fig 9. 6.7.3 Termination control In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated to 0.5 × disabled due to an overload condition both pins become floating. 6.7.4 Bus, RXD and TXD failure detection The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in All failures are signalled separately in the CANFD bits in the System Diagnosis register ...

Page 23

... NXP Semiconductors 6.7.4.3 GND shift detection The SBC can detect ground shifts in reference to the CAN-bus. Two different ground shift detection levels can be selected with the GSTHC bit in the Configuration register. The failure can be read out in the System Diagnosis register. Any detected or recovered GND shift event is signalled with an interrupt, if enabled ...

Page 24

... NXP Semiconductors The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. When leaving Active mode the LIN transmitter is disabled and the LIN receiver is monitoring the LIN-bus for a valid wake-up. 6.8.1.2 Off-line mode Off-line mode is the low-power mode of the LIN transceiver ...

Page 25

... NXP Semiconductors During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN provides an internal switch to BAT42. For master and slave operation an external resistor, 1 kΩ kΩ respectively, can be applied between pins RTLIN and LIN. An external diode in series with the termination resistor is not required due to the incorporated internal diode ...

Page 26

... NXP Semiconductors INH/LIMP: HIGH ILEN = 1 ILC = 1 state change via SPI Fig 13. States of the INH/LIMP pin When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a default LOW level. The pin can be set to HIGH according to the state diagram. When pin INH/LIMP is used as limp-home output, a pull-up resistor to V default HIGH level ...

Page 27

... NXP Semiconductors su(CS) sample active signal already HIGH V WAKE due to biasing (history) flip flop V INTN Fig 14. Pin WAKE, cyclic sampling via V3 6.11 Interrupt output Pin INTN is an open-drain interrupt output forced LOW whenever at least one bit in the Interrupt register is set. By reading the Interrupt register all bits are cleared. The Interrupt register will also be cleared during a system reset (RSTN LOW) ...

Page 28

... NXP Semiconductors 6.13 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content ...

Page 29

... NXP Semiconductors To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures: • SPI clock count failure (wrong number of clock cycles during one SPI access): only 16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock cycles results in an SPI failure interrupt, if enabled ...

Page 30

... NXP Semiconductors 6.13.3 Mode register In the Mode register the watchdog is defined and re-triggered, and the SBC operating mode is selected. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) control bit. During system operation cyclic access to the Mode register is required to serve the watchdog ...

Page 31

... NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 00 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 01 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 10 (as set in the Special Mode register) ...

Page 32

... NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 11 (as set in the Special Mode register) [1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f [2] See Section 6 ...

Page 33

... NXP Semiconductors Table 7. System Status register bit description Bit Symbol Description RSS[3:0] Reset Source 7 CWS CAN Wake-up Status 6 LWS LIN Wake-up Status 5 EWS Edge Wake-up Status 4 WLS WAKE Level Status 3 TWS Temperature Warning Status 2 SDMS Software Development Mode Status 1 ENS Enable Status ...

Page 34

... NXP Semiconductors 6.13.5 System Diagnosis register This register allows diagnosis information to be read back from the SBC. This register can be read in all modes. Table 8. System Diagnosis register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO ...

Page 35

... NXP Semiconductors Table 8. System Diagnosis register bit description Bit Symbol Description 1 and 0 CANMD [1:0] CAN Mode Diagnosis [1] V2D will be set when V2 is reactivated after a failure. See 6.13.6 Interrupt Enable register and Interrupt Enable Feedback register These registers allow setting, clearing and reading back the interrupt enable bits of the SBC ...

Page 36

... NXP Semiconductors Table 9. Interrupt Enable and Interrupt Enable Feedback register bit description Bit Symbol Description 3 WIE WAKE Interrupt Enable 2 WDRIE Watchdog Restart Interrupt Enable 1 CANIE CAN Interrupt Enable 0 LINIE LIN Interrupt Enable [1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required (fail-safe behavior) ...

Page 37

... NXP Semiconductors Table 10. Interrupt register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 WTI Watchdog Time-out Interrupt 10 OTI OverTemperature Interrupt 9 GSI Ground Shift Interrupt 8 SPIFI SPI clock count Failure Interrupt 7 BATFI BAT Failure Interrupt ...

Page 38

... NXP Semiconductors 6.13.8 System Configuration register and System Configuration Feedback register These registers allow configuration of the behavior of the SBC, and allow the settings to be read back. Table 11. System Configuration and System Configuration Feedback register bit description Bit Symbol Description 15 and 14 A1, A0 ...

Page 39

... NXP Semiconductors 6.13.9 Physical Layer Control register and Physical Layer Control Feedback register These registers allow configuration of the CAN transceiver and LIN transceiver of the SBC and allow the settings to be read back. Table 12. Physical Layer Control and Physical Layer Control Feedback register bit description ...

Page 40

... NXP Semiconductors [3] In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the LTC bit under software control. ...

Page 41

... NXP Semiconductors 6.13.11 General Purpose registers and General Purpose Feedback registers The UJA1065 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a ‘ ...

Page 42

... NXP Semiconductors Table 16. System Status register: status at reset Symbol Name RSS Reset Source Status CWS CAN Wake-up Status LWS LIN Wake-up Status EWS Edge Wake-up Status WLS WAKE Level Status TWS Temperature Warning Status SDMS Software Development Mode Status ENS Enable Status ...

Page 43

... NXP Semiconductors Table 20. System Configuration register and System Configuration Feedback register: status at reset Symbol Name GSTHC GND Shift level Threshold Control RLC Reset Length Control V3C V3 Control V1CMC V1 Current Monitor Control WEN Wake Enable WSC Wake Sample Control ILEN INH/LIMP Enable ...

Page 44

... NXP Semiconductors Table 22. Special Mode register: status at reset Symbol Name ISDM Initialize Software Development Mode ERREM Error pin emulation mode WDPRE Watchdog Prescale Factor V1RTHC V1 Reset Threshold Control Table 23. General Purpose register 0 and General Purpose Feedback register 0: status at reset Symbol Name ...

Page 45

... NXP Semiconductors There are two possibilities to enter Software development mode. One is by setting the ISDM bit via the Special Mode register; possible only once after a first battery connection while the SBC is in Start-up mode. The second possibility to enter Software development mode is by applying the correct V applied to pin BAT42 ...

Page 46

... ESD performance according to IEC 61000-4 150 pF 330 Ω) of pins CANH, CANL, RTH, RTL, LIN, RTLIN, WAKE, BAT42 [4] and V3 with respect to GND was verified by an external test house. Following results were obtained: a) Equal or better than ±4 kV (unaided) b) Equal or better than ±20 kV (using external ESD protection: NXP Semiconductors PESD1CAN and PESD1LIN diode) Machine Model (MM 200 pF 0.75 μ Ω. [5] UJA1065_7 ...

Page 47

... NXP Semiconductors 8. Thermal characteristics Fig 16. Thermal model of the HTSSOP32 package 9. Static characteristics Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Supply; pin BAT42 I BAT42 supply BAT42 current I additional BAT42 ...

Page 48

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter V BAT42 voltage level POR(BAT42) for power-on reset status bit change Supply; pin BAT14 I BAT14 supply BAT14 current I additional BAT14 ...

Page 49

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter ΔV supply voltage V1 regulation load regulation voltage drift with temperature V undervoltage det(UV)(V1) detection and reset activation level V undervoltage ...

Page 50

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter [4] Voltage source; pin V2 V output voltage o(V2) ΔV supply voltage V2 regulation load regulation voltage drift with temperature I output current ...

Page 51

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Serial peripheral interface inputs; pins SDI, SCK and SCS V HIGH-level input IH(th) threshold voltage V LOW-level input IL(th) threshold voltage ...

Page 52

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter R TXDC pull-up TXDC(pu) resistor CAN receive data output; pin RXDC I HIGH-level output OH current I LOW-level output OL current High-speed CAN-bus lines; pins CANH and CANL ...

Page 53

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I CANL dominant o(CANL)(dom) output current I recessive output o(reces) current R input resistance i R input resistance i(m) matching R differential input ...

Page 54

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I LOW-level output OL current LIN-bus line; pin LIN V LIN dominant output o(dom) voltage I HIGH-level input LIH leakage current I LOW-level input ...

Page 55

... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter ΔV RTLIN load RTLIN regulation I RTLIN pull-up RTLIN(pu) current I LOW-level leakage LL current TEST input; pin TEST V input threshold ...

Page 56

... NXP Semiconductors Fig 17. V1 output voltage (dropout function of battery voltage UJA1065_7 Product data sheet ( −100 μA −50 mA −120 mA −250 ° ( −100 μA −50 mA −120 mA −250 150 °C. j Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip type 5V0 type 3V3 ...

Page 57

... NXP Semiconductors I BAT14 (mA) (1) Types 5V0 and 3V3. (2) Type 5V0 only BAT14 (mA) (1) Types 5V0 and 3V3. (2) Type 3V3 only Fig 18. V1 quiescent current as a function of output current UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip 10 − ( BAT14 2 (2) 5 ...

Page 58

... NXP Semiconductors Fig 19. V1 output voltage as a function of output current PSRR (dB) (1) Type 5V0 only. Fig 20. V1 power supply ripple rejection as a function of frequency UJA1065_7 Product data sheet 6 type 5V0 V V1 (V) 4 type 3V3 2 0 − BAT14 = 25 °C to 125 ° 160 ...

Page 59

... NXP Semiconductors V BAT14 a. Line transient response (mA) b. Load transient response Fig 21. V1 transient response as a function of time UJA1065_7 Product data sheet 16 (V) V BAT14 100 200 = −5 mA μF; ESR = 0.01 Ω − − 100 200 = μF; ESR = 0.01 Ω BAT14 Rev. 07 — 25 February 2010 ...

Page 60

... NXP Semiconductors ESR Fig 22. V1 output stability related to ESR value of output capacitor UJA1065_7 Product data sheet 1 (Ω) −1 10 −2 10 unstable operation area −3 10 −40 0 Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip stable operation area −80 I (mA) V1 UJA1065 001aaf249 − ...

Page 61

... NXP Semiconductors a. Switch-on test circuit. b. Behavior Behavior at T Fig 23. Switch-on behavior of V UJA1065_7 Product data sheet BAT42 BAT14 100 μF/ V BAT 0.1 Ω 100 ( BAT V = 5.5 V BAT BAT ° ( BAT 5.5 V BAT BAT ° Rev. 07 — 25 February 2010 High-speed CAN/LIN fail-safe system basis chip ...

Page 62

... NXP Semiconductors 10. Dynamic characteristics Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see T clock cycle time cyc t enable lead time ...

Page 63

... NXP Semiconductors Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter t maximum time before off-line entering Off-line mode t extended minimum time off-line(ext) before entering Off-line mode LIN transceiver; pins LIN, TXDL and RXDL δ ...

Page 64

... NXP Semiconductors Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Power supply V1; pin clamped LOW time V1(CLT) during ramp- Power supply V2; pin clamped LOW time V2(CLT) during ramp- Power supply V3 ...

Page 65

... NXP Semiconductors Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Interrupt output; pin INTN t interrupt release INTN Oscillator f oscillator frequency osc All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient [1] temperature on wafer level (pretesting). Cased products are 100 % tested at 25 ° ...

Page 66

... NXP Semiconductors Fig 25. Timing test circuit for CAN transceiver Fig 26. Timing diagram CAN transceiver UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip BAT42 RXDC 10 pF TXDC GND TXDC CANH CANL V o(dif) RXDC t t(reces-dom) t PHL Rev. 07 — 25 February 2010 UJA1065 ...

Page 67

... NXP Semiconductors Fig 27. Timing test circuit for LIN transceiver t bit V TXDL V BAT42 LIN BUS signal V RXDL1 receiving node 1 t p(rx)f V RXDL2 receiving node 2 Fig 28. Timing diagram LIN transceiver 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications ...

Page 68

... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 ...

Page 69

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 70

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 71

... NXP Semiconductors Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1065_7 Product data sheet High-speed CAN/LIN fail-safe system basis chip maximum peak temperature = MSL limit, damage level ...

Page 72

... NXP Semiconductors 14. Revision history Table 30. Revision history Document ID Release date UJA1065_7 20100225 • Modifications: 3.0 V version (UJA1065TW/3V0) discontinued • Section • Table 11: text of bit 4, V1CMC, revised • Section • Section UJA1065_6 20071122 UJA1065_5 20061116 UJA1065_4 20060818 UJA1065_3 20060221 UJA1065_2 20051216 UJA1065_1 ...

Page 73

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 74

... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 75

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Power management . . . . . . . . . . . . . . . . . . . . . 3 2.5 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 Introduction 6.2 Fail-safe system controller ...

Page 76

... NXP Semiconductors 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 68 13 Soldering of SMD packages . . . . . . . . . . . . . . 69 13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 69 13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 69 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 69 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 70 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 72 15 Legal information 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 73 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ...