PDI1394P25BD ST-Ericsson Inc, PDI1394P25BD Datasheet - Page 40

• Manufacturer Part Number: PDI1394P25BD
• Description: IC IEEE 1394 LINK CTRLR 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394P25BD

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 64-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. LPS reasserted. After the interface has been in the reset or
2. SYSCLK activated. If the interface is disabled, the PHY
1. LPS reasserted. After the interface has been in the reset or
2. SYSCLK activated. If the interface is disabled, the PHY
Philips Semiconductors
The sequence of events for initialization of the PHY-LLC interface
when the interface is in the differentiated mode of operation (ISO
terminal is low) is as follows:
The sequence of events for initialization of the PHY-LLC interface
when the interface is in the non-differentiated mode of operation
(ISO terminal is high) is as follows:
2001 Sep 06
1-port 400 Mbps physical layer interface
disabled state for at least the minimum T
causes the interface to be initialized and restored to normal
operation by re-activating the LPS signal. (In the above diagram,
the interface is shown in the disabled state with SYSCLK
high-impedance inactive. However, the interface initialization
sequence described here is also executed if the interface is
merely reset but not yet disabled.)
re-activates its SYSCLK output when it detects that LPS has
been reasserted. SYSCLK will be restored within 60 ns. The
PHY commences SYSCLK activity by driving the SYSCLK output
low for half a cycle. Thereafter, the SYSCLK output is a 50%
duty cycle square wave with a frequency of 49.152 MHz +100
disabled state for at least the minimum T
causes the interface to be initialized and restored to normal
operation by reasserting the LPS signal. (In the above diagram,
the interface is shown in the disabled state with SYSCLK low
inactive. However, the interface initialization sequence described
here is also executed if the interface is merely reset but not yet
disabled.)
re-activates its SYSCLK output when it detects that LPS has
been reasserted. SYSCLK will be restored within 60 ns. The
SYSCLK output is a 50% duty cycle square wave with a
frequency of 49.152 MHz +100 ppm (period of 20.345 ns).
SYSCLK
D0 – D7
LREQ
CTL0
CTL1
LPS
ISO
(high)
(a)
T
CLK_ACTIVATE
RESTORE
RESTORE
Figure 25. Interface Initialization, ISO High
time, the LLC
time, the LLC
(b)
7 cycles
39
3. Receive indicated. Upon the eighth SYSCLK cycle following
4. Initialization complete. The PHY asserts the Idle state on the
3. Receive indicated. Upon the eighth SYSCLK cycle following
4. Initialization complete. The PHY asserts the Idle state on the
ppm (period of 20.345 ns). Upon the first full cycle of SYSCLK,
the PHY drives the CTL and D terminals low for one cycle. The
LLC is also required to drive its CTL, D, and LREQ outputs low
during one of the first six cycles of SYSCLK (in the above
diagram, this is shown as occurring in the first SYSCLK cycle).
reassertion of LPS, the PHY asserts the Receive state on the
CTL lines and the data-on indication (all ones) on the D lines for
one or more cycles (because the interface is in the differentiated
mode of operation, the CTL and D lines will be in the
high-impedance state after the first cycle).
CTL lines and logic 0 on the D lines. This indicates that the
PHY-LLC interface initialization is complete and normal operation
may commence. The PHY will now accept requests from the
LLC via the LREQ line.
During the first seven cycles of SYSCLK, the PHY continues to
drive the CTL and D terminals low. The LLC is also required to
drive its CTL and D outputs low for one of the first six cycles of
SYSCLK but to otherwise place its CTL and D outputs in a
high-impedance state. The LLC continues to drive its LREQ
output low during this time.
reassertion of LPS, the PHY asserts the Receive state on the
CTL lines and the data-on indication (all ones) on the D lines for
one or more cycles.
CTL lines and logic 0 on the D lines. This indicates that the
PHY-LLC interface initialization is complete and normal operation
may commence. The PHY will now accept requests from the
LLC via the LREQ line.
(c)
PDI1394P25
Preliminary data
SV01815