PDI1394P25BD ST-Ericsson Inc, PDI1394P25BD Datasheet - Page 36

• Manufacturer Part Number: PDI1394P25BD
• Description: IC IEEE 1394 LINK CTRLR 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394P25BD

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 64-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Normal operation. Interface is operating normally, with LPS
2. LPS deasserted. The LLC deasserts the LPS signal and, within
Philips Semiconductors
The sequence of events for resetting the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
2001 Sep 06
1-port 400 Mbps physical layer interface
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via the
LREQ line.
1.0 ms, terminates any request or interface bus activity, and
places its LREQ, CTL, and D outputs into a high-impedance
state (the LLC should terminate any output signal activity such
that signals end in a logic 0 state).
CTL0, CTL1
SYSCLK
D0 – D7
LREQ
LPS
ISO
(high)
(a)
Figure 21. Interface Reset, ISO High
(b)
T
LPS_RESET
35
3. Interface reset. After T
4. Interface restored. After the minimum T
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
may again assert LPS active. (The minimum T
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described on the next page.
(c)
T
RESTORE
LPS_RESET
time, the PHY determines that
(d)
RESTORE
PDI1394P25
RESTORE
time, the LLC
Preliminary data
SV01811
interval