ISP1563BMUM ST-Ericsson Inc, ISP1563BMUM Datasheet - Page 79

• Manufacturer Part Number: ISP1563BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-T; ISP1563BM-T

Philips Semiconductors
Table 106: USBINTR - USB Interrupt Enable register bit allocation
Address: Value read from func2 of address 10h + 28h
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
Table 107: USBINTR - USB Interrupt Enable register bit description
Address: Value read from func2 of address 10h + 28h
Bit
31 to 6
5
4
3
2
1
0
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
reserved
IAAE
HSEE
FLRE
PCIE
USBERRI
NTE
USBINTE
IAAE
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
-
Interrupt on Asynchronous Advance Enable: When this bit and IAA
(bit 5 in the USBSTS register) are set, the Host Controller issues an
interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing bit IAA.
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS
register) are set, the Host Controller issues an interrupt. The interrupt is
acknowledged by software clearing bit HSE.
Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS
register) are set, the Host Controller issues an interrupt. The interrupt is
acknowledged by software clearing bit FLR.
Port Change Interrupt Enable: When this bit and PCD (bit 2 in the
USBSTS register) are set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit PCD.
USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the
USBSTS register) are set, the Host Controller issues an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software
clearing bit USBERRINT.
USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS
register) are set, the Host Controller issues an interrupt at the next
interrupt threshold. The interrupt is acknowledged by software clearing
bit USBINT.
Rev. 01 — 14 July 2005
HSEE
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
FLRE
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
PCIE
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
USBERR
INTE
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
ISP1563
USBINTE
R/W
R/W
R/W
R/W
79 of 107
24
16
0
0
8
0
0
0