ISP1563BMUM ST-Ericsson Inc, ISP1563BMUM Datasheet - Page 26

• Manufacturer Part Number: ISP1563BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-T; ISP1563BM-T

Philips Semiconductors
Table 27:
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
8.2.2.2 FLADJ register
8.2.2.3 PORTWAKECAP register
R/W
7
0
reserved
Table 26:
Legend: * reset value
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in
Table 28:
Port Wake Capability (PORTWAKECAP) is a 2 B register used to establish a policy about
which ports are for wake events; see
correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit
position indicates that a device connected below the port can be enabled as a wake-up
device and the port may be enabled for disconnect or connect, or overcurrent events as
wake-up events. This is an information only mask register. The bits in this register do not
affect the actual operation of the EHCI Host Controller. The system-specific policy can be
Bit
7 to 0
Bit
7 to 6
5 to 0
[1]
R/W
6
0
Symbol
SBRN[7:0]
Table
Symbol
reserved
FLADJ[5:0]
SBRN - Serial Bus Release Number register (address 60h) bit description
FLADJ - Frame Length Adjustment register (address 61h) bit description
27.
R/W
Access
R
5
1
Description
-
Frame Length Timing Value: Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time (number of
SOF counter clock periods to generate a SOF micro frame length) is
equal to 59488 + value in this field. The default value is decimal 32 (20h),
which gives a SOF cycle time of 60000.
Rev. 01 — 14 July 2005
Value
20h*
R/W
FLADJ value
4
0
31 (1Fh)
32 (20h)
62 (3Eh)
63 (3Fh)
0 (00h)
1 (01h)
2 (02h)
Table
:
:
Description
Serial Bus Specification Release Number: This
register value is to identify Serial Bus Specification
Rev. 2.0. All other combinations are reserved.
29. Bit positions 15 to 1 in the mask
R/W
3
0
FLADJ[5:0]
R/W
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
SOF cycle time (480 MHz)
R/W
59488
59504
59520
59984
60000
60480
60496
1
0
:
:
ISP1563
R/W
26 of 107
0
0