ISP1563BMUM ST-Ericsson Inc, ISP1563BMUM Datasheet - Page 44

• Manufacturer Part Number: ISP1563BMUM
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-T; ISP1563BM-T

Philips Semiconductors
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
reserved
R/W
R/W
R/W
23
15
0
0
7
0
[1]
Table 49:
Bit
31
30
29 to 7
6
5
4
3
2
1
0
Address: Value read from func0 or func1 of address 10h + 0Ch
RHSC
R/W
R/W
R/W
22
14
0
0
6
0
Symbol
reserved
OC
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptStatus - Host Controller Interrupt Status register bit description
FNO
R/W
R/W
R/W
Description
-
Ownership Change: This bit is set by the Host Controller when the HCD
sets OCR (bit 3) in the HcCommandStatus register. This event, when
unmasked, will always immediately generate a System Management
Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not
implemented.
-
Root Hub Status Change: This bit is set when the content of HcRhStatus or
the content of any of HcRhPortStatus[NumberofDownstreamPort] has
changed.
Frame Number Overflow: This bit is set when the MSB of HcFmNumber
(bit 15) changes value, or after HccaFrameNumber is updated.
Unrecoverable Error: This bit is set when the Host Controller detects a
system error not related to USB. The Host Controller should not proceed with
any processing nor signaling before the system error is corrected. The HCD
clears this bit after the Host Controller is reset.
Resume Detected: This bit is set when the Host Controller detects that a
device on the USB is asserting resume signaling. This bit is set by the
transition from no resume signaling to resume signaling. This bit is not set
when the HCD sets the USBRESUME state.
Start-of-Frame: At the start of each frame, this bit is set by the Host
Controller and an SOF token is generated at the same time.
Write-back Done Head: This bit is immediately set after the Host Controller
has written HcDoneHead to HccaDoneHead. Further, updates of
HccaDoneHead occur only after this bit is cleared. The HCD should only
clear this bit after it has saved the content of HccaDoneHead.
Scheduling Overrun: This bit is set when USB schedules for current frame
overruns and after the update of HccaFrameNumber. A scheduling overrun
increments the SOC[1:0] field (bits 17 to 16 of HcCommandStatus).
21
13
0
0
5
0
Rev. 01 — 14 July 2005
R/W
R/W
R/W
UE
20
12
0
0
4
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
RD
19
11
0
0
3
0
R/W
R/W
R/W
SF
18
10
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
WDH
R/W
R/W
R/W
17
0
9
0
1
0
ISP1563
R/W
R/W
R/W
44 of 107
SO
16
0
8
0
0
0