ISP1562BEUM ST-Ericsson Inc, ISP1562BEUM Datasheet - Page 43

• Manufacturer Part Number: ISP1562BEUM
• Description: IC USB HOST CTRL HI-SPD 100LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1562BEUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1562BE-T; ISP1562BE-T

NXP Semiconductors
Table 55.
Address: Content of the base address register + 18h
[1]
Table 56.
Address: Content of the base address register + 18h
ISP1562_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 0
The reserved bits should always be written with the reset value.
Symbol
HCCA[23:0]
reserved
HcHCCA - Host Controller Communication Area register bit allocation
HcHCCA - Host Controller Communication Area register bit description
11.1.7 HcHCCA register
11.1.8 HcPeriodCurrentED register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
The HcHCCA register contains the physical address of Host Controller Communication
Area (HCCA). The bit allocation is given in
restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The
alignment is evaluated by examining the number of zeroes in lower order bits. The
minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0
when read. This area is used to hold the control structures and the interrupt table that are
accessed by both the Host Controller and the HCD.
Description
Host Controller Communication Area Base Address: This is the base address of the HCCA.
-
The HcPeriodCurrentED register contains the physical address of the current isochronous
or interrupt ED.
Table 57
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 02 — 1 March 2007
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
HCCA[23:16]
HCCA[15:8]
HCCA[7:0]
reserved
[1]
Table
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
55. The HCD determines alignment
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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