ISP1562BEUM ST-Ericsson Inc, ISP1562BEUM Datasheet - Page 41

• Manufacturer Part Number: ISP1562BEUM
• Description: IC USB HOST CTRL HI-SPD 100LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1562BEUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1562BE-T; ISP1562BE-T

NXP Semiconductors
Table 52.
Address: Content of the base address register + 10h
Table 53.
Address: Content of the base address register + 14h
ISP1562_2
Product data sheet
Bit
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptEnable - Host Controller Interrupt Enable register bit description
HcInterruptDisable - Host Controller Interrupt Disable register bit allocation
11.1.6 HcInterruptDisable register
R/W
R/W
MIE
31
23
0
0
Description
Root Hub Status Change:
0 — Ignore
1 — Enables interrupt generation because of root hub status change.
Frame Number Overflow:
0 — Ignore
1 — Enables interrupt generation because of frame number overflow.
Unrecoverable Error:
0 — Ignore
1 — Enables interrupt generation because of unrecoverable error.
Resume Detect:
0 — Ignore
1 — Enables interrupt generation because of resume detect.
Start-of-Frame:
0 — Ignore
1 — Enables interrupt generation because of Start-of-Frame.
HcDoneHead Write-back:
0 — Ignore
1 — Enables interrupt generation because of HcDoneHead write-back.
Scheduling Overrun:
0 — Ignore
1 — Enables interrupt generation because of scheduling overrun.
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this
register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a
read, the current value of the HcInterruptEnable register is returned.
The register contains 4 bytes, and the bit allocation is given in
R/W
R/W
OC
30
22
0
0
R/W
R/W
29
21
0
0
Rev. 02 — 1 March 2007
R/W
R/W
28
20
0
0
reserved
[1]
R/W
R/W
27
19
0
0
reserved
[1]
R/W
R/W
26
18
0
0
HS USB PCI Host Controller
…continued
Table
53.
R/W
R/W
25
17
0
0
© NXP B.V. 2007. All rights reserved.
ISP1562
R/W
R/W
24
16
0
0
40 of 93