DS33X161+ Maxim Integrated Products, DS33X161+ Datasheet - Page 276

• Manufacturer Part Number: DS33X161+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X161+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 12: Loopback Mode (LM) - When set to 1, all frames destined for the transmit GMII/MII/RMII interface are
internally transferred to the receive GMII/MII/RMII. Frames received on the GMII/MII/RMII are not transferred to the
transmit GMII/MII/RMII interface. Note that there is no SA/DA swapping performed. If SA/DA swapping of LAN
traffic is required, the LAN extract/insertion functions must be used.
Bit 11: Duplex Mode (DM) - When set to 1, the MAC transmits and receives simultaneously (full-duplex).
Bit 9: Disable Retry (DRTY) - When set to 1, the MAC makes only a single attempt to transmit each frame. If a
collision occurs, the MAC ignores the current frame, reports a Frame Abort, reports an excessive collision error,
and proceeds to the next frame. When this bit equals 0, the MAC will retry collided frames based on the settings in
the Backoff Limit bits before signaling a retry error. This bit is applicable to half-duplex mode only.
Bit 8: Automatic Pad Stripping (APST) - When set to 1, all incoming frames with less than 46 byte length are
automatically stripped of the pad characters and FCS. When equal to zero, all frames are received unmodified.
Bit 7: Automatic CRC Stripping (ACST) - When set to 1, the MAC will strip the FCS field on incoming frames only
if the length field is less than or equal to 1500 bytes. All received frames with length field greater than 1500 bytes
will be passed to the receiver without stripping of the FCS field. When equal to zero, all frames are received
unmodified. For most applications of this device, this bit should equal 0.
Bits 5 - 6: Back-Off Limit (BOLMT[1:0])- These two bits allow the user to set the back-off limit used for the
maximum retransmission delay for collided frames. Default operation limits the maximum delay for retransmission
to a countdown of 10 bits from a random number generator. The user can reduce the maximum number of counter
bits as described in the table below. See IEEE 802.3 for details of the back-off algorithm.
Bit 7
Bit 4: Deferral Check (DC) - When set to 1, the MAC will abort frame transmission if it has deferred for more than
24,288 bit times. The deferral counter starts when the transmitter is ready to transmit a frame, but is prevented
from transmission because RX_CRS is active. If the MAC begins transmission but a collision occurs after the
beginning of transmission, the deferral counter is reset again. If this bit is equal to zero, then the MAC will defer
indefinitely.
Bit 3: Transmitter Enable (TE) - When set to 1, frame transmission is enabled. When equal to zero, transmission
is disabled.
Bit 2: Receiver Enable (RE) - When set to 1, frame reception is enabled. When equal to zero, frames are not
received.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0
0
1
1
Bit 6
0
1
0
1
Random Number Generator Bits Used
10
8
4
1
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