DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 37

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3
The clock sources and functions are as follows:
The device expects gapped clocks for T3/E3/T1/E1 data streams, minimally gapped for line overhead periods
The following table provides the different clocking options for the Ethernet interface.
Table 8-1. Clocking Options for the Ethernet Interface
*
Rev: 063008
Clock sources should be accurate to
TX_CLKn Frequency
RX_CLKn Frequency
REF_CLK Frequency
GTX_CLK
MDC Output Clock Frequency
RMII_SEL Input Pin
GL.CR1.P1SPD /
GL.CR1.P2SPD
SU.MACCR.GMIIMIIS
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
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Clock Structure
Serial Transmit Data (TCLKn) and Serial Receive Data (RCLKn) clock inputs are used to transfer data from
the serial interface. These clocks can be continuous or gapped.
The Serial Transmit Clock for ports 9-12 is a shared clock (TMCLK3). The Serial Transmit Sync for ports 9-
12 is also shared (TMSYNC3).
The Serial Transmit Clock for ports 13-16 is a shared clock (TMCLK4). The Serial Transmit Sync for ports
13-16 is also shared (TMSYNC4).
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with +/- 100 ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SD_CLK pin for the operation of the SDRAM.
The Transmit and Receive clocks for the MII/RMII Interface (TX_CLK and RX_CLK). In DTE mode, these
are input pins and accept clocks provided by an Ethernet PHY.
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.
Ethernet Interface Mode
±
Speed
100ppm.
MII
100Mbps
25MHz
25MHz
25MHz
N/A
1.67MHz
0
1
1
MII
10Mbps
2.5MHz
2.5MHz
25MHz
N/A
1.67MHz
0
0
1
RMII
10/100 Mbps
N/A
N/A
50MHz
N/A
1.67MHz
1
0=10Mbps
1=100Mbps
1
GMII
1000 Mbps
N/A
125MHz
125MHz
125MHz
1.67MHz
0
N/A
0
I/O
I/O
Input
Output
Output
Input
Register
Register
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