DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 164

IC MAPPING ETHERNET 256CSBGA

DS33X81+

Manufacturer Part Number
DS33X81+
Description
IC MAPPING ETHERNET 256CSBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS33X81+

Applications
Data Transport
Interface
Parallel/Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
256-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10.3 Ethernet Interface Registers
The Ethernet Interface registers are used to configure GMII/MII/RMII bus operation and establish the MAC
parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The
registers below are used to perform indirect read or write operations to the MAC registers. The MAC Status
Registers are shown in Table 10-3. Accessing the MAC Registers is described in Section 8.19.
10.3.1 WAN Extraction and Transmit LAN registers
Register Name:
Register Description:
Register Address:
0A0h:
Default
WAN Extract Modes. This register determines which set of WAN Trap modes have been enabled. The WAN Trap
modes can be unrelated to the LAN Trap modes in the opposite direction. Any combination of these Traps can be
enabled. If any enabled Trap Modes overlap so that the WAN Trap indicates that a frame should be forwarded to
an Ethernet Port and to the WAN Extract, the frame is to be only forwarded to the WAN Extract (e.g. the user might
have configured the WAN Trap to forward the frame’s VLAN ID to Ethernet Port 1, but the frame’s DA might also
indicate that the frame is to be sent to the WAN Extract). WAN VLAN/Q-in-Q Forwarding is enabled through the
Forwarding Mode (not through these registers). The default setting is all Modes disabled.
Bit 9: WAN Extract Management Address Trap (WMGMTT)
Bit 8: WAN Extract Broadcast Address Trap (WBAT)
Bit 7: WAN “No VLAN/Q-in-Q” Detected Forwarding (WNVDF).
To configure the X162 for VLAN or Q-in-Q, WAN to LAN forwarding, the Forwarding Mode must be set to 5, and
the WETPID register must be configured (or use the configuration register default values).
Bit 6: WAN Extract FIFO Reset (WEFR)
Rev: 063008
0A1h:
Default
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0 = WAN Extract Management Address Trap is disabled.
1 = WAN Extract Management Address Trap is enabled. All Ethernet frames with an Ethernet Destination
Address (DA) = 01:80:C2:xx:xx:xx, where “x” is “don’t care,” are forwarded to the WAN extract queue.
0 = WAN Extract Broadcast Address Trap is disabled.
1 = WAN Extract Broadcast Address Trap is enabled. All Ethernet frames with an Ethernet Destination
Address (DA) = FF:FF:FF:FF:FF:FF are forwarded to the WAN extract queue.
0 = When the 13
forwarded to Ethernet Interface 1.
1 = When the 13
forwarded to Ethernet Interface 2.
0 = Normal – no reset.
1 = One-time, momentary reset of the WAN Extract FIFO.
WNVDF
Bit 15
Bit 7
0
0
-
th
th
WEFR
Bit 14
and 14
and 14
Bit 6
0
0
-
th
th
SU.WEM
WAN Extract Modes and Ethernet Tag Settings
0A0h
bytes in the frame do not equate to the value in WETPID, then the frame is to be
bytes in the frame do not equate to the value in WETPID, then the frame is to be
WEDS2
Bit 13
Bit 5
0
0
-
WEDS1
Bit 12
Bit 4
0
0
-
WEVIT
Bit 11
Bit 3
0
0
-
WEETT
Bit 10
Bit 2
0
0
-
WMGMTT
WEDAT
Bit 9
Bit 1
0
0
164 of 375
WBAT
WEHT
Bit 8
Bit 0
0
0

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