DS33W41+ Maxim Integrated Products, DS33W41+ Datasheet - Page 269

• Manufacturer Part Number: DS33W41+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33W41+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

641h:
Default
10.8.3 Transmit Per Serial Port Register Description
Register Name:
Register Description:
Register Address:
640h:
Default
Bit 4: TMCLKm/TCLKn Invert (TCLKINV) Note: Valid for m = 1 to 4, n = 1 to 8.
Bits 1-2: TSYNC Setup (TS_SETUP[1:0]). These two bits accommodate a TSYNC signal that arrives earlier
than the start of frame.
TS_SETUP[1:0]
00
01
10
11
Bit 0: TDATA Select (TD_SEL).
TMCLKn / TMSYNCn
Assignment when
TD_SEL=0
TMCLK1 / TMSYNC1
TMCLK2 / TMSYNC2
TMCLK3 / TMSYNC3*
TMCLK4 / TMSYNC4*
* Note: For serial ports 9-16, the TD_SEL bit is not available. Ports 9-16 must use TMCLKn and TMSYNCn.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0 = TMCLKm/TCLKn is not inverted
1 = TMCLKm/TCLKn is inverted
0 = TDATAn is referenced to the associated TMCLKn, TMSYNCn.
1 = TDATAn is referenced to the associated TCLKn, TSYNCn. Not valid for Serial Ports 9-16.
Bit 15
Bit 7
0
0
-
-
Bit 14
Bit 6
1-4
5-8
Ports
9-12*
13-16*
0
0
-
-
LI.TCR
Serial Interface Transmit Control Register
640h (+ 008h x (n-1), Physical Serial Port n=1 to 16)
TSYNC Arrives
0 cycles early
1 cycle early
2 cycles early
3 cycles early
Bit 13
Bit 5
0
0
-
-
TCLKINV
Bit 12
Bit 4
0
0
-
Bit 11
Bit 3
0
0
-
-
TS_SETUP1 TS_SETUP0
Bit 10
Bit 2
0
0
-
Bit 9
Bit 1
0
0
-
TD_SEL
269 of 375
Bit 8
Bit 0
0
0
-